Simon Pilgrim 29a89e51e6 [X86][SSE] Add load-folding patterns for (V)CVTDQ2PD (PR27291) ...

Added patterns for (V)CVTDQ2PD -> 2f64 loading from a 64-bit source.

llvm-svn: 271269

2016-05-31 12:04:35 +00:00

..

AArch64

[AArch64] Generate rev16/rev32 from bswap + srl when upper bits are known zero.

2016-05-26 19:41:33 +00:00

AMDGPU

AMDGPU: Cleanup vector insert/extract tests

2016-05-28 00:51:06 +00:00

ARM

Fix default reloc model on ARM.

2016-05-28 10:41:15 +00:00

BPF

[BPF] Remove exit-on-error from tests (PR27768, PR27769)

2016-05-30 08:28:34 +00:00

Generic

llc: Rework -run-pass option

2016-05-10 01:32:44 +00:00

Hexagon

[Hexagon] Enable the post-RA scheduler

2016-05-26 19:44:28 +00:00

Inputs

[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.

2016-04-15 15:57:41 +00:00

Lanai

[lanai] Change reloc to use PIC_ by default and cleanup.

2016-05-20 21:41:53 +00:00

Mips

[mips] bnec/beqc register constraint fix

2016-05-31 09:54:55 +00:00

MIR

Add test/CodeGen/MIR/Hexagon/lit.local.cfg

2016-05-26 18:35:45 +00:00

MSP430

…

NVPTX

[NVPTX] Added NVVMIntrRange pass

2016-05-26 17:02:56 +00:00

PowerPC

Move and add comments to the top for tailcall-string-rvo.ll

2016-05-25 17:01:09 +00:00

SPARC

[SPARC] Fix 8 and 16-bit atomic load and store.

2016-05-23 20:33:00 +00:00

SystemZ

[SystemZ] Fix register ordering for BinaryRRF instructions

2016-05-18 13:24:57 +00:00

Thumb

ARM: stop emitting blx instructions for most calls on MachO.

2016-05-10 19:17:47 +00:00

Thumb2

ARM: stop emitting blx instructions for most calls on MachO.

2016-05-10 19:17:47 +00:00

WebAssembly

[WebAssembly] Put __stack_pointer in the offset field of loads and stores.

2016-05-24 23:47:41 +00:00

WinEH

[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.

2016-04-15 15:57:41 +00:00

X86

[X86][SSE] Add load-folding patterns for (V)CVTDQ2PD (PR27291)

2016-05-31 12:04:35 +00:00

XCore

[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.

2016-04-15 15:57:41 +00:00