Jun Bum Lim 28eed32332 [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth() ...

Summary:
This change will allow loads with imp-def to be clustered in machine-scheduler pass.
areMemAccessesTriviallyDisjoint() can also handle loads with imp-def.

Reviewers: mcrosier, jmolloy, t.p.northover

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D18665

llvm-svn: 265051

2016-03-31 20:53:47 +00:00

..

cfi-def-cfa.mir

When printing MIR, output to errs() rather than outs().

2016-02-19 00:18:46 +00:00

expected-target-flag-name.mir

MIR Serialization: Serialize the operand's bit mask target flags.

2015-08-18 22:52:15 +00:00

invalid-target-flag-name.mir

MIR Serialization: Serialize the operand's bit mask target flags.

2015-08-18 22:52:15 +00:00

lit.local.cfg

…

machine-dead-copy.mir

Introduce MachineFunctionProperties and the AllVRegsAllocated property

2016-03-28 17:05:30 +00:00

machine-scheduler.mir

[AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()

2016-03-31 20:53:47 +00:00

multiple-lhs-operands.mir

When printing MIR, output to errs() rather than outs().

2016-02-19 00:18:46 +00:00

stack-object-local-offset.mir

fix CHECK_NEXT -> CHECK-NEXT

2016-03-28 22:03:07 +00:00

target-flags.mir

When printing MIR, output to errs() rather than outs().

2016-02-19 00:18:46 +00:00