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695f1e65cb
For fcmp, major concern about the following 6 cases is NaN result. The comparison result consists of 4 bits, indicating lt, eq, gt and un (unordered), only one of which will be set. The result is generated by fcmpu instruction. However, bc instruction only inspects one of the first 3 bits, so when un is set, bc instruction may jump to to an undesired place. More specifically, if we expect an unordered comparison and un is set, we expect to always go to true branch; in such case UEQ, UGT and ULT still give false, which are undesired; but UNE, UGE, ULE happen to give true, since they are tested by inspecting !eq, !lt, !gt, respectively. Similarly, for ordered comparison, when un is set, we always expect the result to be false. In such case OGT, OLT and OEQ is good, since they are actually testing GT, LT, and EQ respectively, which are false. OGE, OLE and ONE are tested through !lt, !gt and !eq, and these are true. llvm-svn: 263753
188 lines
2.7 KiB
LLVM
188 lines
2.7 KiB
LLVM
; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
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define i1 @TestULT(double %t0) {
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; CHECK-LABEL: TestULT:
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; CHECK: mcrf
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; CHECK: blr
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entry:
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%t1 = fcmp ult double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestULE(double %t0) {
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; CHECK-LABEL: TestULE:
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; CHECK: fcmpu
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; CHECK-NEXT: ble
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; CHECK: blr
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entry:
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%t1 = fcmp ule double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestUNE(double %t0) {
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; CHECK-LABEL: TestUNE:
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; CHECK: fcmpu
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; CHECK-NEXT: bne
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; CHECK: blr
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entry:
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%t1 = fcmp une double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestUEQ(double %t0) {
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; CHECK-LABEL: TestUEQ:
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; CHECK: mcrf
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; CHECK: blr
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entry:
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%t1 = fcmp ueq double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestUGT(double %t0) {
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; CHECK-LABEL: TestUGT:
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; CHECK: mcrf
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; CHECK: blr
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entry:
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%t1 = fcmp ugt double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestUGE(double %t0) {
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; CHECK-LABEL: TestUGE:
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; CHECK: fcmpu
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; CHECK-NEXT: bge
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; CHECK: blr
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entry:
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%t1 = fcmp uge double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOLT(double %t0) {
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; CHECK-LABEL: TestOLT:
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; CHECK: fcmpu
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; CHECK-NEXT: blt
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; CHECK: blr
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entry:
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%t1 = fcmp olt double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOLE(double %t0) {
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; CHECK-LABEL: TestOLE:
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; CHECK: mcrf
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; CHECK: blr
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entry:
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%t1 = fcmp ole double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestONE(double %t0) {
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; CHECK-LABEL: TestONE:
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; CHECK: mcrf
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; CHECK: blr
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entry:
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%t1 = fcmp one double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOEQ(double %t0) {
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; CHECK-LABEL: TestOEQ:
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; CHECK: fcmpu
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; CHECK-NEXT: beq
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; CHECK: blr
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entry:
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%t1 = fcmp oeq double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOGT(double %t0) {
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; CHECK-LABEL: TestOGT:
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; CHECK: fcmpu
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; CHECK-NEXT: bgt
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; CHECK: blr
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entry:
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%t1 = fcmp ogt double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOGE(double %t0) {
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; CHECK-LABEL: TestOGE:
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; CHECK: mcrf
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; CHECK: blr
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entry:
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%t1 = fcmp oge double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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