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7d64810efd
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
41 lines
1.5 KiB
LLVM
41 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=armv7--eabi -verify-machineinstrs < %s | FileCheck %s
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; Check the way we schedule/merge a bunch of loads and stores.
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; Originally test/CodeGen/ARM/2011-07-07-ScheduleDAGCrash.ll ; now
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; being used as a test of optimizations related to ldm/stm.
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; FIXME: We could merge more loads/stores with regalloc hints.
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; FIXME: Fix scheduling so we don't have 16 live registers.
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define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp {
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entry:
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%c = load i256, i256* %cc
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%d = load i256, i256* %dd
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%add = add nsw i256 %c, %d
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store i256 %add, i256* %a, align 8
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%or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376
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%add6 = add nsw i256 %or, %d
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store i256 %add6, i256* %b, align 8
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ret void
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; CHECK-DAG: ldm r2
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; CHECK-DAG: ldr {{.*}}, [r3]
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; CHECK-DAG: ldr {{.*}}, [r3, #4]
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; CHECK-DAG: ldr {{.*}}, [r3, #8]
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; CHECK-DAG: ldr {{.*}}, [r3, #12]
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; CHECK-DAG: ldr {{.*}}, [r3, #16]
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; CHECK-DAG: ldr {{.*}}, [r3, #20]
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; CHECK-DAG: ldr {{.*}}, [r3, #24]
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; CHECK-DAG: ldr {{.*}}, [r3, #28]
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; CHECK-DAG: ldr {{.*}}, [r2, #20]
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; CHECK-DAG: ldr {{.*}}, [r2, #24]
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; CHECK-DAG: ldr {{.*}}, [r2, #28]
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; CHECK-DAG: stm r0
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; CHECK-DAG: str {{.*}}, [r0, #20]
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; CHECK-DAG: str {{.*}}, [r0, #24]
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; CHECK-DAG: str {{.*}}, [r0, #28]
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; CHECK-DAG: stm r1
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; CHECK-DAG: str {{.*}}, [r1, #20]
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; CHECK-DAG: str {{.*}}, [r1, #24]
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; CHECK-DAG: str {{.*}}, [r1, #28]
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}
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