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https://github.com/RPCS3/llvm-mirror.git
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e25ded1888
I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
124 lines
3.0 KiB
LLVM
124 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
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; These tests use cmp+adc/sbb in place of test+set+add/sub. Should this transform
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; be enabled by micro-architecture rather than as part of generic lowering/isel?
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define i8 @test1(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpb %sil, %dil
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; CHECK-NEXT: adcb $0, %sil
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%cmp = icmp ult i8 %a, %b
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%cond = zext i1 %cmp to i8
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%add = add i8 %cond, %b
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ret i8 %add
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}
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define i32 @test2(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpl %esi, %edi
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; CHECK-NEXT: adcl $0, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%cmp = icmp ult i32 %a, %b
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%cond = zext i1 %cmp to i32
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%add = add i32 %cond, %b
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ret i32 %add
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}
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define i64 @test3(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpq %rsi, %rdi
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; CHECK-NEXT: adcq $0, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%cmp = icmp ult i64 %a, %b
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%conv = zext i1 %cmp to i64
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%add = add i64 %conv, %b
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ret i64 %add
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}
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define i8 @test4(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpb %sil, %dil
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; CHECK-NEXT: sbbb $0, %sil
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%cmp = icmp ult i8 %a, %b
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%cond = zext i1 %cmp to i8
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%sub = sub i8 %b, %cond
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ret i8 %sub
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}
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define i32 @test5(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpl %esi, %edi
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; CHECK-NEXT: sbbl $0, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%cmp = icmp ult i32 %a, %b
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%cond = zext i1 %cmp to i32
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%sub = sub i32 %b, %cond
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ret i32 %sub
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}
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define i64 @test6(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: test6:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpq %rsi, %rdi
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; CHECK-NEXT: sbbq $0, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%cmp = icmp ult i64 %a, %b
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%conv = zext i1 %cmp to i64
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%sub = sub i64 %b, %conv
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ret i64 %sub
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}
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define i8 @test7(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: test7:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpb %sil, %dil
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; CHECK-NEXT: adcb $0, %sil
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%cmp = icmp ult i8 %a, %b
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%cond = sext i1 %cmp to i8
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%sub = sub i8 %b, %cond
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ret i8 %sub
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}
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define i32 @test8(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: test8:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpl %esi, %edi
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; CHECK-NEXT: adcl $0, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%cmp = icmp ult i32 %a, %b
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%cond = sext i1 %cmp to i32
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%sub = sub i32 %b, %cond
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ret i32 %sub
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}
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define i64 @test9(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: test9:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpq %rsi, %rdi
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; CHECK-NEXT: adcq $0, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%cmp = icmp ult i64 %a, %b
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%conv = sext i1 %cmp to i64
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%sub = sub i64 %b, %conv
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ret i64 %sub
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}
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