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4b4c372886
This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
45 lines
1.2 KiB
LLVM
45 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -o - -O0 < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @test1(i32 %x) #0 {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: andb $1, %al
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; CHECK-NEXT: movzbl %al, %edi
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; CHECK-NEXT: callq callee1
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: retq
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entry:
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%tobool = icmp ne i32 %x, 0
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call void @callee1(i1 zeroext %tobool)
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ret void
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}
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define void @test2(i32 %x) #0 {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: movzbl %al, %edi
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: negl %edi
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; CHECK-NEXT: callq callee2
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: retq
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entry:
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%tobool = icmp ne i32 %x, 0
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call void @callee2(i1 signext %tobool)
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ret void
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}
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declare void @callee1(i1 zeroext)
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declare void @callee2(i1 signext)
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attributes #0 = { nounwind "target-cpu"="skylake-avx512" }
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