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4cbc84cfa7
Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
160 lines
5.9 KiB
LLVM
160 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
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; A single 16-bit load + a single 16-bit store
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define void @load_2_i8(<2 x i8>* %A) {
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; SSE2-LABEL: load_2_i8:
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; SSE2: # BB#0:
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; SSE2-NEXT: movzwl (%rdi), %eax
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; SSE2-NEXT: movd %eax, %xmm0
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
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; SSE2-NEXT: paddq {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: movw %ax, (%rdi)
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: load_2_i8:
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; SSE41: # BB#0:
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; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
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; SSE41-NEXT: paddq {{.*}}(%rip), %xmm0
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,8,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
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; SSE41-NEXT: pextrw $0, %xmm0, (%rdi)
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; SSE41-NEXT: retq
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%T = load <2 x i8>, <2 x i8>* %A
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%G = add <2 x i8> %T, <i8 9, i8 7>
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store <2 x i8> %G, <2 x i8>* %A
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ret void
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}
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; Read 32-bits
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define void @load_2_i16(<2 x i16>* %A) {
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; SSE2-LABEL: load_2_i16:
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; SSE2: # BB#0:
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; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7]
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; SSE2-NEXT: paddq {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; SSE2-NEXT: movd %xmm0, (%rdi)
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: load_2_i16:
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; SSE41: # BB#0:
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; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; SSE41-NEXT: paddq {{.*}}(%rip), %xmm0
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE41-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; SSE41-NEXT: movd %xmm0, (%rdi)
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; SSE41-NEXT: retq
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%T = load <2 x i16>, <2 x i16>* %A
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%G = add <2 x i16> %T, <i16 9, i16 7>
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store <2 x i16> %G, <2 x i16>* %A
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ret void
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}
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define void @load_2_i32(<2 x i32>* %A) {
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; SSE2-LABEL: load_2_i32:
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; SSE2: # BB#0:
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; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
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; SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: movq %xmm0, (%rdi)
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: load_2_i32:
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; SSE41: # BB#0:
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; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
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; SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE41-NEXT: movq %xmm0, (%rdi)
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; SSE41-NEXT: retq
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%T = load <2 x i32>, <2 x i32>* %A
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%G = add <2 x i32> %T, <i32 9, i32 7>
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store <2 x i32> %G, <2 x i32>* %A
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ret void
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}
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define void @load_4_i8(<4 x i8>* %A) {
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; SSE2-LABEL: load_4_i8:
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; SSE2: # BB#0:
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; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: movd %xmm0, (%rdi)
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: load_4_i8:
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; SSE41: # BB#0:
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; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
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; SSE41-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
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; SSE41-NEXT: movd %xmm0, (%rdi)
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; SSE41-NEXT: retq
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%T = load <4 x i8>, <4 x i8>* %A
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%G = add <4 x i8> %T, <i8 1, i8 4, i8 9, i8 7>
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store <4 x i8> %G, <4 x i8>* %A
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ret void
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}
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define void @load_4_i16(<4 x i16>* %A) {
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; SSE2-LABEL: load_4_i16:
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; SSE2: # BB#0:
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; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE2-NEXT: paddw {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: movq %xmm0, (%rdi)
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: load_4_i16:
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; SSE41: # BB#0:
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; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
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; SSE41-NEXT: paddw {{.*}}(%rip), %xmm0
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; SSE41-NEXT: movq %xmm0, (%rdi)
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; SSE41-NEXT: retq
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%T = load <4 x i16>, <4 x i16>* %A
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%G = add <4 x i16> %T, <i16 1, i16 4, i16 9, i16 7>
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store <4 x i16> %G, <4 x i16>* %A
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ret void
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}
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define void @load_8_i8(<8 x i8>* %A) {
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; SSE2-LABEL: load_8_i8:
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; SSE2: # BB#0:
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; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSE2-NEXT: paddb %xmm0, %xmm0
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: movq %xmm0, (%rdi)
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: load_8_i8:
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; SSE41: # BB#0:
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
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; SSE41-NEXT: paddb %xmm0, %xmm0
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
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; SSE41-NEXT: movq %xmm0, (%rdi)
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; SSE41-NEXT: retq
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%T = load <8 x i8>, <8 x i8>* %A
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%G = add <8 x i8> %T, %T
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store <8 x i8> %G, <8 x i8>* %A
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ret void
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}
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