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llvm-mirror/test/CodeGen/Mips
Bjorn Pettersson 29ffba4b56 Update @llvm.powi to handle different int sizes for the exponent
This can be seen as a follow up to commit 0ee439b705e82a4fe20e2,
that changed the second argument of __powidf2, __powisf2 and
__powitf2 in compiler-rt from si_int to int. That was to align with
how those runtimes are defined in libgcc.
One thing that seem to have been missing in that patch was to make
sure that the rest of LLVM also handle that the argument now depends
on the size of int (not using the si_int machine mode for 32-bit).
When using __builtin_powi for a target with 16-bit int clang crashed.
And when emitting libcalls to those rtlib functions, typically when
lowering @llvm.powi), the backend would always prepare the exponent
argument as an i32 which caused miscompiles when the rtlib was
compiled with 16-bit int.

The solution used here is to use an overloaded type for the second
argument in @llvm.powi. This way clang can use the "correct" type
when lowering __builtin_powi, and then later when emitting the libcall
it is assumed that the type used in @llvm.powi matches the rtlib
function.

One thing that needed some extra attention was that when vectorizing
calls several passes did not support that several arguments could
be overloaded in the intrinsics. This patch allows overload of a
scalar operand by adding hasVectorInstrinsicOverloadedScalarOpd, with
an entry for powi.

Differential Revision: https://reviews.llvm.org/D99439
2021-06-17 09:38:28 +02:00
..
cconv [SelectionDAG] Improve scalarization of irregular vector types 2021-03-11 19:57:13 +01:00
compactbranches
cstmaterialization
Fast-ISel Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
GlobalISel [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
indirect-jump-hazard
instverify
llvm-ir [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM. 2021-02-21 11:13:36 -08:00
longbranch
micromips-sizereduction
mips32r6
mips64r6
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msa Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
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atomic.ll [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics 2021-05-20 20:34:23 +01:00
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mips16_32_7.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
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mips16_32_9.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
mips16_32_10.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
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