Stelios Ioannou 4da00eddbe [LSR] Fix for pre-indexed generated constant offset ... This patch changed the isLegalUse check to ensure that LSRInstance::GenerateConstantOffsetsImpl generates an offset that results in a legal addressing mode and formula. The check is changed to look similar to the assert check used for illegal formulas. Differential Revision: https://reviews.llvm.org/D100383 Change-Id: Iffb9e32d59df96b8f072c00f6c339108159a009a		2021-04-15 16:44:42 +01:00
..
AArch64	[AArch64][NEON] Match (or (and -a b) (and (a+1) b)) => bit select	2021-04-15 13:52:47 +01:00
AMDGPU	[LSR] Fix for pre-indexed generated constant offset	2021-04-15 16:44:42 +01:00
ARC
ARM	StackProtector: ensure protection does not interfere with tail call frame.	2021-04-13 15:14:57 +01:00
AVR
BPF	BPF: remove default .extern data section	2021-04-13 11:35:52 -07:00
Generic	[Debug-Info] make fortran CHARACTER(1) type as valid unsigned type	2021-04-11 23:17:01 -04:00
Hexagon
Inputs
Lanai
M68k
Mips
MIR	[AMDGPU] Set implicit arg attributes for indirect calls	2021-04-13 13:15:13 +00:00
MSP430
NVPTX
PowerPC	[AIX] Allow safe for 32bit P8 VSX pattern matching	2021-04-14 08:12:48 -04:00
RISCV	[RISCV] Pre-commit vector shuffle test cases	2021-04-15 10:31:13 +01:00
SPARC
SystemZ
Thumb
Thumb2	[ARM] Add a number of intrinsics for MVE lane interleaving	2021-04-12 17:23:02 +01:00
VE
WebAssembly	[WebAssembly] Codegen for i64x2.extend_{low,high}_i32x4_{s,u}	2021-04-14 13:43:09 -07:00
WinCFGuard
WinEH
X86	[X86] combineCMP - fold cmpEQ/NE(TRUNC(X),0) -> cmpEQ/NE(X,0)	2021-04-15 13:55:51 +01:00
XCore