mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
17e932c916
This adds a combine for extract(x, n); extract(x, n+1) -> VMOVRRD(extract x, n/2). This allows two vector lanes to be moved at the same time in a single instruction, and thanks to the other VMOVRRD folds we have added recently can help reduce the amount of executed instructions. Floating point types are very similar, but will include a bitcast to an integer type. This also adds a shouldRewriteCopySrc, to prevent copy propagation from DPR to SPR, which can break as not all DPR regs can be extracted from directly. Otherwise the machine verifier is unhappy. Differential Revision: https://reviews.llvm.org/D100244
464 lines
14 KiB
LLVM
464 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpeqz_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.i32 ne, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp eq <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpnez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.i32 eq, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp ne <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpsltz_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.s32 ge, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp slt <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpsgtz_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.s32 le, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp sgt <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpslez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.s32 gt, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp sle <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpsgez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.s32 lt, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp sge <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpultz_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp ult <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpugtz_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.i32 eq, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp ugt <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpulez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.u32 cs, q1, zr
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp ule <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpugez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp uge <4 x i32> %b, zeroinitializer
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpeq_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.i32 ne, q1, q2
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp eq <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpne_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.i32 eq, q1, q2
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp ne <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpslt_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.s32 le, q2, q1
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp slt <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpsgt_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.s32 le, q1, q2
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp sgt <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpsle_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.s32 lt, q2, q1
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp sle <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpsge_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i32 ne, q0, zr
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; CHECK-NEXT: vcmpt.s32 lt, q1, q2
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp sge <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpult_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.u32 hi, q2, q1
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp ult <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpugt_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.u32 hi, q1, q2
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp ugt <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpule_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.u32 cs, q2, q1
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp ule <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: cmpuge_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.u32 cs, q1, q2
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%c2 = icmp uge <4 x i32> %b, %c
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%o = or <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: cmpeqz_v8i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i16 ne, q0, zr
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; CHECK-NEXT: vcmpt.i16 ne, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <8 x i16> %a, zeroinitializer
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%c2 = icmp eq <8 x i16> %b, zeroinitializer
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%o = or <8 x i1> %c1, %c2
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%s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %s
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}
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define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: cmpeq_v8i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i16 ne, q0, zr
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; CHECK-NEXT: vcmpt.i16 ne, q1, q2
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <8 x i16> %a, zeroinitializer
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%c2 = icmp eq <8 x i16> %b, %c
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%o = or <8 x i1> %c1, %c2
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%s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %s
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}
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define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: cmpeqz_v16i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i8 ne, q0, zr
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; CHECK-NEXT: vcmpt.i8 ne, q1, zr
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <16 x i8> %a, zeroinitializer
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%c2 = icmp eq <16 x i8> %b, zeroinitializer
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%o = or <16 x i1> %c1, %c2
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%s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %s
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}
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define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
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; CHECK-LABEL: cmpeq_v16i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i8 ne, q0, zr
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; CHECK-NEXT: vcmpt.i8 ne, q1, q2
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <16 x i8> %a, zeroinitializer
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%c2 = icmp eq <16 x i8> %b, %c
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%o = or <16 x i1> %c1, %c2
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%s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %s
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}
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define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: cmpeqz_v2i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, r1, d3
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; CHECK-NEXT: orrs r0, r1
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; CHECK-NEXT: vmov r1, r2, d2
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; CHECK-NEXT: cset r0, eq
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: orrs r1, r2
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; CHECK-NEXT: cset r1, eq
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
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; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
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; CHECK-NEXT: vmov r0, r1, d1
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; CHECK-NEXT: orrs r0, r1
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; CHECK-NEXT: vmov r1, r2, d0
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; CHECK-NEXT: cset r0, eq
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: orrs r1, r2
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; CHECK-NEXT: cset r1, eq
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
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; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
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; CHECK-NEXT: vorr q2, q3, q2
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; CHECK-NEXT: vbic q1, q1, q2
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; CHECK-NEXT: vand q0, q0, q2
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; CHECK-NEXT: vorr q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <2 x i64> %a, zeroinitializer
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%c2 = icmp eq <2 x i64> %b, zeroinitializer
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%o = or <2 x i1> %c1, %c2
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%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %s
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}
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define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
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; CHECK-LABEL: cmpeq_v2i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, r1, d5
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; CHECK-NEXT: vmov r2, r3, d3
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; CHECK-NEXT: eors r0, r2
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; CHECK-NEXT: eors r1, r3
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; CHECK-NEXT: orrs r0, r1
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; CHECK-NEXT: vmov r12, r2, d4
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; CHECK-NEXT: vmov r3, r1, d2
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; CHECK-NEXT: cset r0, eq
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: eors r1, r2
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; CHECK-NEXT: eor.w r2, r3, r12
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; CHECK-NEXT: orrs r1, r2
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; CHECK-NEXT: cset r1, eq
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
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; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
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; CHECK-NEXT: vmov r0, r1, d1
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; CHECK-NEXT: orrs r0, r1
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; CHECK-NEXT: vmov r1, r2, d0
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; CHECK-NEXT: cset r0, eq
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: orrs r1, r2
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; CHECK-NEXT: cset r1, eq
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
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; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
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; CHECK-NEXT: vorr q2, q3, q2
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; CHECK-NEXT: vbic q1, q1, q2
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; CHECK-NEXT: vand q0, q0, q2
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; CHECK-NEXT: vorr q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <2 x i64> %a, zeroinitializer
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%c2 = icmp eq <2 x i64> %b, %c
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%o = or <2 x i1> %c1, %c2
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%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %s
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}
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