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LowOverheadLoops
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[ARM][LowOverheadLoops] Make some stack spills valid for tail predication
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2021-07-15 19:23:52 +01:00 |
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mve-intrinsics
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2009-07-17-CrossRegClassCopy.ll
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2009-07-21-ISelBug.ll
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2009-07-23-CPIslandBug.ll
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2009-07-30-PEICrash.ll
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2009-08-01-WrongLDRBOpc.ll
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2009-08-02-CoalescerBug.ll
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2009-08-04-CoalescerAssert.ll
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2009-08-04-CoalescerBug.ll
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[SimplifyCFG] Teach removeUndefIntroducingPredecessor to preserve DomTree
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2021-01-02 01:01:20 +03:00 |
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2009-08-04-ScavengerAssert.ll
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2009-08-04-SubregLoweringBug2.ll
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2009-08-04-SubregLoweringBug3.ll
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2009-08-04-SubregLoweringBug.ll
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2009-08-06-SpDecBug.ll
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2009-08-07-CoalescerBug.ll
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2009-08-07-NeonFPBug.ll
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2009-08-08-ScavengerAssert.ll
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2009-08-10-ISelBug.ll
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2009-08-21-PostRAKill4.ll
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2009-09-01-PostRAProlog.ll
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2009-10-15-ITBlockBranch.ll
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2009-11-01-CopyReg2RegBug.ll
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2009-11-11-ScavengerAssert.ll
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2009-11-13-STRDBug.ll
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2009-12-01-LoopIVUsers.ll
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2010-01-06-TailDuplicateLabels.ll
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2010-01-19-RemovePredicates.ll
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2010-02-11-phi-cycle.ll
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[CPG][ARM] Optimize towards branch on zero in codegenprepare
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2021-05-16 17:54:06 +01:00 |
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2010-02-24-BigStack.ll
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2010-03-08-addi12-ccout.ll
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2010-03-15-AsmCCClobber.ll
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2010-04-15-DynAllocBug.ll
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2010-04-26-CopyRegCrash.ll
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2010-05-24-rsbs.ll
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2010-06-14-NEONCoalescer.ll
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2010-06-19-ITBlockCrash.ll
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2010-06-21-TailMergeBug.ll
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2010-08-10-VarSizedAllocaBug.ll
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2010-11-22-EpilogueBug.ll
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2010-12-03-AddSPNarrowing.ll
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2011-04-21-FILoweringBug.ll
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2011-06-07-TwoAddrEarlyClobber.ll
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2011-12-16-T2SizeReduceAssert.ll
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2012-01-13-CBNZBug.ll
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2013-02-19-tail-call-register-hint.ll
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2013-03-02-vduplane-nonconstant-source-index.ll
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2013-03-06-vector-sext-operand-scalarize.ll
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aapcs.ll
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active_lane_mask.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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aligned-constants.ll
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aligned-nonfallthrough.ll
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[ARM] Remove DLS lr, lr
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2021-02-02 11:09:31 +00:00 |
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aligned-spill.ll
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bfi.ll
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bfx.ll
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bicbfi.ll
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block-placement.mir
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[ARM] Extra widening and narrowing combinations tests. NFC
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2021-07-10 22:08:30 +01:00 |
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bug-subw.ll
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buildvector-crash.ll
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call-site-info-update.ll
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carry.ll
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cbnz.ll
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cde-gpr.ll
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cde-vec.ll
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cde-vfp.ll
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cmp-frame.ll
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constant-hoisting.ll
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constant-islands-cbz.ll
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constant-islands-cbz.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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constant-islands-cbzundef.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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constant-islands-jump-table.ll
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constant-islands-ldrsb.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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constant-islands-new-island-padding.ll
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constant-islands-new-island.ll
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constant-islands.ll
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cortex-fp.ll
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crash.ll
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cross-rc-coalescing-1.ll
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cross-rc-coalescing-2.ll
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csel.ll
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[ARM] Ensure CSINC has one use in CSINV combine
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2021-04-29 10:59:14 +01:00 |
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div.ll
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emit-unwinding.ll
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fir.ll
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float-cmp.ll
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float-intrinsics-double.ll
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Update @llvm.powi to handle different int sizes for the exponent
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2021-06-17 09:38:28 +02:00 |
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float-intrinsics-float.ll
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Update @llvm.powi to handle different int sizes for the exponent
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2021-06-17 09:38:28 +02:00 |
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float-ops.ll
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fp16-stacksplot.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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frame-index-addrmode-t2i8s4.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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frame-pointer.ll
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frameless2.ll
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frameless.ll
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high-reg-spill.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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ifcvt-cbz.mir
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ifcvt-compare.ll
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ifcvt-dead-predicate.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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ifcvt-minsize.ll
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ifcvt-neon-deprecated.mir
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ifcvt-no-branch-predictor.ll
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ifcvt-rescan-bug-2016-08-22.ll
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ifcvt-rescan-diamonds.ll
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[Local] Do not introduce a new llvm.trap before unreachable
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2021-07-26 23:33:36 -05:00 |
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inflate-regs.ll
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inline-asm-i-constraint-i1.ll
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inlineasm-error-t-toofewregs-mve.ll
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inlineasm-mve.ll
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inlineasm.ll
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intrinsics-cc.ll
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Update @llvm.powi to handle different int sizes for the exponent
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2021-06-17 09:38:28 +02:00 |
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intrinsics-coprocessor.ll
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large-call.ll
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large-stack.ll
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ldr-str-imm12.ll
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lit.local.cfg
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longMACt.ll
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lsll0.ll
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[ARM] Ensure instructions are simplified prior to GatherScatter lowering.
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2021-06-10 20:18:12 +01:00 |
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lsr-deficiency.ll
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m4-sched-ldr.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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m4-sched-regs.ll
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machine-licm.ll
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mul_const.ll
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mve-abs.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-basic.ll
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mve-be.ll
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[ARM] VECTOR_REG_CAST undef -> undef
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2021-02-28 11:13:49 +00:00 |
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mve-bitarith.ll
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mve-bitcasts.ll
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mve-bitreverse.ll
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mve-blockplacement.ll
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[ARM] Remove dead mov's in preheader of tail predicated loops
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2021-02-11 10:48:20 +00:00 |
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mve-bswap.ll
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mve-ctlz.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-ctpop.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-cttz.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-div-expand.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-extractelt.ll
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mve-extractstore.ll
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[ARM] Optimize fp store of extract to integer store if already available.
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2021-02-12 18:34:58 +00:00 |
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mve-float16regloops.ll
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[ARM] Simplification to ARMBlockPlacement Pass.
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2021-05-06 01:20:18 +01:00 |
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mve-float32regloops.ll
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[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
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2021-06-11 16:49:12 +01:00 |
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mve-fma-loops.ll
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[ARM] Clean up some tests, removing dead instructions. NFC
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2021-05-22 13:38:00 +01:00 |
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mve-fmas.ll
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[ARM] KnownBits for CSINC/CSNEG/CSINV
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2021-03-04 08:40:20 +00:00 |
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mve-fmath.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-fp16convertloops.ll
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[ARM] Generate VDUP(Const) from constant buildvectors
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2021-06-08 20:51:33 +01:00 |
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mve-fp-negabs.ll
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[ARM] Select VINS from vector inserts
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2021-02-02 13:50:02 +00:00 |
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mve-frint.ll
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[ARM] Select VINS from vector inserts
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2021-02-02 13:50:02 +00:00 |
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mve-gather-increment.ll
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[ARM] Introduce MVEEXT ISel lowering
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2021-07-13 07:21:20 +01:00 |
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mve-gather-ind8-unscaled.ll
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[ARM] Lower non-extended small gathers via truncated gathers.
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2021-07-17 22:38:31 +01:00 |
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mve-gather-ind16-scaled.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-gather-ind16-unscaled.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-gather-ind32-scaled.ll
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[ARM] Add some opaque pointer gather/scatter tests. NFC
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2021-07-07 22:03:53 +01:00 |
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mve-gather-ind32-unscaled.ll
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[ARM] Add some opaque pointer gather/scatter tests. NFC
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2021-07-07 22:03:53 +01:00 |
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mve-gather-optimisation-deep.ll
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[ARM] Guard against loop variant gather ptr operands
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2021-05-30 18:02:14 +01:00 |
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mve-gather-ptrs.ll
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[ARM] Lower non-extended small gathers via truncated gathers.
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2021-07-17 22:38:31 +01:00 |
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mve-gather-scatter-opt.ll
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[ARM] Add some opaque pointer gather/scatter tests. NFC
|
2021-07-07 22:03:53 +01:00 |
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mve-gather-scatter-optimisation.ll
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[ARM] Add some opaque pointer gather/scatter tests. NFC
|
2021-07-07 22:03:53 +01:00 |
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mve-gather-scatter-ptr-address.ll
|
[ARM] Add some opaque pointer gather/scatter tests. NFC
|
2021-07-07 22:03:53 +01:00 |
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mve-gather-scatter-tailpred.ll
|
[ARM] Add some opaque pointer gather/scatter tests. NFC
|
2021-07-07 22:03:53 +01:00 |
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mve-gather-tailpred.ll
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[ARM] Don't handle low overhead branches in AnalyzeBranch
|
2021-01-18 17:16:07 +00:00 |
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mve-gather-unused.ll
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[ARM] Ensure instructions are simplified prior to GatherScatter lowering.
|
2021-06-10 20:18:12 +01:00 |
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mve-gatherscatter-mmo.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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mve-halving.ll
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mve-laneinterleaving-cost.ll
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[ARM] Create VMOVRRD from adjacent vector extracts
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2021-04-20 15:15:43 +01:00 |
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mve-laneinterleaving.ll
|
[ARM] Introduce MVEEXT ISel lowering
|
2021-07-13 07:21:20 +01:00 |
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mve-ldst-offset.ll
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mve-ldst-postinc.ll
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mve-ldst-preinc.ll
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mve-ldst-regimm.ll
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mve-loadstore.ll
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mve-masked-ldst-offset.ll
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mve-masked-ldst-postinc.ll
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mve-masked-ldst-preinc.ll
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mve-masked-ldst.ll
|
[ARM] Move double vector insert patterns using vins to DAG combine
|
2021-02-22 09:29:47 +00:00 |
|
mve-masked-load.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-masked-store.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
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mve-memtp-branch.ll
|
[ARM] Allow findLoopPreheader to return headers with multiple loop successors
|
2021-05-24 12:22:15 +01:00 |
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mve-memtp-loop.ll
|
[ARM] Introduce t2WhileLoopStartTP
|
2021-06-13 13:55:34 +01:00 |
|
mve-minmax.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
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mve-multivec-spill.ll
|
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
|
2021-06-11 16:49:12 +01:00 |
|
mve-neg.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-nofloat.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-nounrolledremainder.ll
|
[ARM] KnownBits for CSINC/CSNEG/CSINV
|
2021-03-04 08:40:20 +00:00 |
|
mve-phireg.ll
|
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
|
2021-06-11 16:49:12 +01:00 |
|
mve-postinc-dct.ll
|
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
|
2021-06-11 16:49:12 +01:00 |
|
mve-postinc-distribute.ll
|
[ARM] Improve WLS lowering
|
2021-03-11 17:56:19 +00:00 |
|
mve-postinc-distribute.mir
|
[ARM] Ensure correct regclass in distributing postinc
|
2021-07-26 14:26:38 +01:00 |
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mve-postinc-lsr.ll
|
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
|
2021-06-11 16:49:12 +01:00 |
|
mve-pred-and.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-pred-bitcast.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-pred-build-const.ll
|
|
|
|
mve-pred-build-var.ll
|
[ARM] Combine sub 0, csinc X, Y, CC -> csinv -X, Y, CC
|
2021-04-16 11:52:31 +01:00 |
|
mve-pred-const.ll
|
|
|
|
mve-pred-constfold.ll
|
[ARM] MVE vcreate tests, for dual lane moves. NFC
|
2020-12-10 09:17:34 +00:00 |
|
mve-pred-convert.ll
|
|
|
|
mve-pred-ext.ll
|
[ARM] Correct type of setcc results for FP vectors
|
2021-06-16 11:11:03 +01:00 |
|
mve-pred-loadstore.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-pred-not.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-pred-or.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-pred-selectop2.ll
|
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|
mve-pred-selectop3.ll
|
|
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|
mve-pred-selectop.ll
|
|
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|
mve-pred-shuffle.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-pred-spill.ll
|
|
|
|
mve-pred-threshold.ll
|
[ARM] Remove DLS lr, lr
|
2021-02-02 11:09:31 +00:00 |
|
mve-pred-vctpvpsel.ll
|
[ARM] Generate VDUP(Const) from constant buildvectors
|
2021-06-08 20:51:33 +01:00 |
|
mve-pred-vselect.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-pred-xor.ll
|
[ARM] Ensure instructions are simplified prior to GatherScatter lowering.
|
2021-06-10 20:18:12 +01:00 |
|
mve-qrintr.ll
|
|
|
|
mve-satmul-loops.ll
|
[ARM] Introduce MVETRUNC ISel lowering
|
2021-06-26 22:00:26 +01:00 |
|
mve-saturating-arith.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-scatter-increment.ll
|
[ARM] Add some opaque pointer gather/scatter tests. NFC
|
2021-07-07 22:03:53 +01:00 |
|
mve-scatter-ind8-unscaled.ll
|
[ARM] Lower MVETRUNC to stack operations
|
2021-06-26 22:12:57 +01:00 |
|
mve-scatter-ind16-scaled.ll
|
[ARM] Rejig some of the MVE gather/scatter lowering pass. NFC
|
2021-06-15 15:38:39 +01:00 |
|
mve-scatter-ind16-unscaled.ll
|
[ARM] Lower MVETRUNC to stack operations
|
2021-06-26 22:12:57 +01:00 |
|
mve-scatter-ind32-scaled.ll
|
[ARM] Use rq gather/scatters for smaller v4 vectors
|
2021-06-15 17:06:15 +01:00 |
|
mve-scatter-ind32-unscaled.ll
|
[ARM] Add some opaque pointer gather/scatter tests. NFC
|
2021-07-07 22:03:53 +01:00 |
|
mve-scatter-ptrs.ll
|
[ARM] Add some opaque pointer gather/scatter tests. NFC
|
2021-07-07 22:03:53 +01:00 |
|
mve-selectcc.ll
|
[ARM] Ensure instructions are simplified prior to GatherScatter lowering.
|
2021-06-10 20:18:12 +01:00 |
|
mve-sext-masked-load.ll
|
|
|
|
mve-sext.ll
|
[ARM] Introduce MVEEXT ISel lowering
|
2021-07-13 07:21:20 +01:00 |
|
mve-shifts-scalar.ll
|
[ARM] Remove DLS lr, lr
|
2021-02-02 11:09:31 +00:00 |
|
mve-shifts.ll
|
[ARM] Generate VDUP(Const) from constant buildvectors
|
2021-06-08 20:51:33 +01:00 |
|
mve-shuffle.ll
|
[ARM] Fold extract of ARM_BUILD_VECTOR
|
2021-06-29 11:03:19 +01:00 |
|
mve-shuffleext.ll
|
[ARM] Introduce MVEEXT ISel lowering
|
2021-07-13 07:21:20 +01:00 |
|
mve-shufflemov.ll
|
[ARM] Move double vector insert patterns using vins to DAG combine
|
2021-02-22 09:29:47 +00:00 |
|
mve-simple-arith.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-soft-float-abi.ll
|
[ARM] Fold extract of ARM_BUILD_VECTOR
|
2021-06-29 11:03:19 +01:00 |
|
mve-stack.ll
|
|
|
|
mve-stacksplot.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
mve-tailpred-loopinvariant.ll
|
[ARM] Recognize VIDUP from BUILDVECTORs of additions
|
2021-04-27 19:33:24 +01:00 |
|
mve-tp-loop.mir
|
[ARM] Fix inline memcpy trip count sequence
|
2021-05-24 11:01:58 +01:00 |
|
mve-vabd.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vabdus.ll
|
[ARM] Introduce MVETRUNC ISel lowering
|
2021-06-26 22:00:26 +01:00 |
|
mve-vaddqr.ll
|
[ARM] Use half directly for args/return types in test. NFC
|
2021-01-25 17:50:19 +00:00 |
|
mve-vaddv.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vcmp.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vcmpf.ll
|
[ARM] KnownBits for CSINC/CSNEG/CSINV
|
2021-03-04 08:40:20 +00:00 |
|
mve-vcmpfr.ll
|
[ARM] KnownBits for CSINC/CSNEG/CSINV
|
2021-03-04 08:40:20 +00:00 |
|
mve-vcmpfz.ll
|
[ARM] KnownBits for CSINC/CSNEG/CSINV
|
2021-03-04 08:40:20 +00:00 |
|
mve-vcmpr.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vcmpz.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vcreate.ll
|
[ARM] Simplify VMOVRRD from extracts of buildvectors
|
2021-02-01 16:09:25 +00:00 |
|
mve-vctp.ll
|
|
|
|
mve-vcvt16.ll
|
|
|
|
mve-vcvt-fixed-to-float.ll
|
[ARM] Transform a floating-point to fixed-point conversion to a VCVT_fix
|
2021-07-01 15:10:40 +01:00 |
|
mve-vcvt-float-to-fixed.ll
|
[ARM] Transform a floating-point to fixed-point conversion to a VCVT_fix
|
2021-07-01 15:10:40 +01:00 |
|
mve-vcvt.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vdup.ll
|
[ARM] Use half directly for args/return types in test. NFC
|
2021-01-25 17:50:19 +00:00 |
|
mve-vecreduce-add.ll
|
[ARM] Extend more reductions during lowering
|
2021-07-19 08:58:03 +01:00 |
|
mve-vecreduce-addpred.ll
|
[ARM] Extend more reductions during lowering
|
2021-07-19 08:58:03 +01:00 |
|
mve-vecreduce-bit.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vecreduce-fadd.ll
|
[ARM] Use half directly for args/return types in test. NFC
|
2021-01-25 17:50:19 +00:00 |
|
mve-vecreduce-fminmax.ll
|
[ARM] Use half directly for args/return types in test. NFC
|
2021-01-25 17:50:19 +00:00 |
|
mve-vecreduce-fmul.ll
|
[ARM] Use half directly for args/return types in test. NFC
|
2021-01-25 17:50:19 +00:00 |
|
mve-vecreduce-loops.ll
|
[ARM] Clean up some tests, removing dead instructions. NFC
|
2021-05-22 13:38:00 +01:00 |
|
mve-vecreduce-mla.ll
|
[ARM] Extend more reductions during lowering
|
2021-07-19 08:58:03 +01:00 |
|
mve-vecreduce-mlapred.ll
|
[ARM] Extend more reductions during lowering
|
2021-07-19 08:58:03 +01:00 |
|
mve-vecreduce-mul.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vector-spill.ll
|
|
|
|
mve-vfma.ll
|
|
|
|
mve-vhadd.ll
|
[ARM] Extra tests for MVE vhadd and vmulh. NFC
|
2021-05-20 14:13:39 +01:00 |
|
mve-vhaddsub.ll
|
|
|
|
mve-vidup.ll
|
[ARM] Recognize VIDUP from BUILDVECTORs of additions
|
2021-04-27 19:33:24 +01:00 |
|
mve-vld2-post.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vld2.ll
|
[ARM] Transfer memory operands for VLDn
|
2021-05-03 00:04:21 +01:00 |
|
mve-vld3.ll
|
[ARM] Fold extract of ARM_BUILD_VECTOR
|
2021-06-29 11:03:19 +01:00 |
|
mve-vld4-post.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vld4.ll
|
[ARM] Fold extract of ARM_BUILD_VECTOR
|
2021-06-29 11:03:19 +01:00 |
|
mve-vldshuffle.ll
|
[ARM] Extend search for increment in load/store optimizer
|
2021-02-15 13:17:21 +00:00 |
|
mve-vldst4.ll
|
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
|
2021-06-11 16:49:12 +01:00 |
|
mve-vmaxnma-commute.ll
|
[ARM] Improve WLS lowering
|
2021-03-11 17:56:19 +00:00 |
|
mve-vmaxv-vminv-scalar.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vmaxv.ll
|
|
|
|
mve-vmla.ll
|
|
|
|
mve-vmovimm.ll
|
[ARM] Generate VDUP(Const) from constant buildvectors
|
2021-06-08 20:51:33 +01:00 |
|
mve-vmovn.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vmovnstore.ll
|
[ARM] Select VINS from vector inserts
|
2021-02-02 13:50:02 +00:00 |
|
mve-vmulh.ll
|
[ARM] Add patterns for vmulh
|
2021-05-26 09:22:12 +01:00 |
|
mve-vmull-loop.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vmull-splat.ll
|
[ARM] Introduce MVEEXT ISel lowering
|
2021-07-13 07:21:20 +01:00 |
|
mve-vmull.ll
|
|
|
|
mve-vmulqr.ll
|
|
|
|
mve-vmvnimm.ll
|
[ARM] Generate VDUP(Const) from constant buildvectors
|
2021-06-08 20:51:33 +01:00 |
|
mve-vpsel.ll
|
|
|
|
mve-vpt-2-blocks-1-pred.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-2-blocks-2-preds.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-2-blocks-ctrl-flow.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-2-blocks-non-consecutive-ins.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-2-blocks.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-3-blocks-kill-vpr.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-block-1-ins.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-block-2-ins.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-block-4-ins.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-block-debug.mir
|
[ARM] Skip debug during vpt block creation
|
2021-06-10 14:49:04 +01:00 |
|
mve-vpt-block-elses.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-block-fold-vcmp.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
mve-vpt-block-kill.mir
|
|
|
|
mve-vpt-block-optnone.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
mve-vpt-blocks.ll
|
|
|
|
mve-vpt-from-intrinsics.ll
|
|
|
|
mve-vpt-nots.mir
|
|
|
|
mve-vpt-optimisations.mir
|
[ARM] Common inverse constant predicates to VPNOT
|
2020-12-09 07:56:44 +00:00 |
|
mve-vpt-preuse.mir
|
|
|
|
mve-vqdmulh.ll
|
[ARM] Expand types handled in VQDMULH recognition
|
2021-07-15 14:47:53 +01:00 |
|
mve-vqmovn-combine.ll
|
|
|
|
mve-vqmovn.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vqshrn.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
mve-vst2-post.ll
|
|
|
|
mve-vst2.ll
|
[ARM] Transfer memory operands for VLDn
|
2021-05-03 00:04:21 +01:00 |
|
mve-vst3.ll
|
[ARM] Fold extract of ARM_BUILD_VECTOR
|
2021-06-29 11:03:19 +01:00 |
|
mve-vst4-post.ll
|
|
|
|
mve-vst4.ll
|
[ARM] Fixup vst4 test. NFC
|
2021-07-26 20:56:22 +01:00 |
|
mve-vsubqr.ll
|
|
|
|
mve-widen-narrow.ll
|
[ARM] Introduce MVEEXT ISel lowering
|
2021-07-13 07:21:20 +01:00 |
|
mve-zext-masked-load.ll
|
[ARM] Create VMOVRRD from adjacent vector extracts
|
2021-04-20 15:15:43 +01:00 |
|
peephole-addsub.mir
|
|
|
|
peephole-cmp.mir
|
|
|
|
phi_prevent_copy.mir
|
[ARM] Prevent phi-node-elimination from generating copy above t2WhileLoopStartLR
|
2021-04-16 16:45:07 +01:00 |
|
pic-load.ll
|
|
|
|
postinc-distribute.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
scavenge-lr.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
schedm7-hazard.ll
|
[ARM] Add bank conflict hazarding
|
2020-12-23 14:00:59 +00:00 |
|
segmented-stacks.ll
|
|
|
|
setjmp_longjmp.ll
|
[NFC][Codegen] Autogenerate Thumb2/setjmp_longjmp.ll test
|
2021-06-24 21:35:05 +03:00 |
|
shift_parts.ll
|
|
|
|
srem-seteq-illegal-types.ll
|
Support {S,U}REMEqFold before legalization
|
2021-04-01 01:35:41 +03:00 |
|
stack_guard_remat.ll
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
store-prepostinc.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
t2-teq-reduce.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
t2peephole-t2ADDrr-to-t2ADDri.ll
|
|
|
|
t2sizereduction.mir
|
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
|
2021-05-24 19:43:40 +02:00 |
|
tail-call-r9.ll
|
|
|
|
tbb-removeadd.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
thumb2-adc.ll
|
|
|
|
thumb2-add2.ll
|
|
|
|
thumb2-add3.ll
|
|
|
|
thumb2-add4.ll
|
|
|
|
thumb2-add5.ll
|
|
|
|
thumb2-add6.ll
|
|
|
|
thumb2-add.ll
|
|
|
|
thumb2-and2.ll
|
|
|
|
thumb2-and.ll
|
|
|
|
thumb2-asr2.ll
|
|
|
|
thumb2-asr.ll
|
|
|
|
thumb2-bcc.ll
|
|
|
|
thumb2-bfc.ll
|
|
|
|
thumb2-bic.ll
|
|
|
|
thumb2-branch.ll
|
|
|
|
thumb2-call-tc.ll
|
|
|
|
thumb2-call.ll
|
|
|
|
thumb2-cbnz.ll
|
|
|
|
thumb2-clz.ll
|
|
|
|
thumb2-cmn2.ll
|
|
|
|
thumb2-cmn.ll
|
|
|
|
thumb2-cmp.ll
|
|
|
|
thumb2-cpsr-liveness.ll
|
|
|
|
thumb2-eor2.ll
|
|
|
|
thumb2-eor.ll
|
|
|
|
thumb2-execute-only-prologue.ll
|
|
|
|
thumb2-ifcvt1-tc.ll
|
|
|
|
thumb2-ifcvt1.ll
|
[SimplifyCFG] Tail-merging all blocks with ret terminator
|
2021-06-24 13:15:39 +03:00 |
|
thumb2-ifcvt2.ll
|
|
|
|
thumb2-ifcvt3.ll
|
|
|
|
thumb2-jtb.ll
|
|
|
|
thumb2-ldm.ll
|
|
|
|
thumb2-ldr_ext.ll
|
|
|
|
thumb2-ldr_post.ll
|
|
|
|
thumb2-ldr_pre.ll
|
|
|
|
thumb2-ldr.ll
|
|
|
|
thumb2-ldrb.ll
|
|
|
|
thumb2-ldrd.ll
|
|
|
|
thumb2-ldrh.ll
|
|
|
|
thumb2-lsl2.ll
|
|
|
|
thumb2-lsl.ll
|
|
|
|
thumb2-lsr2.ll
|
|
|
|
thumb2-lsr3.ll
|
|
|
|
thumb2-lsr.ll
|
|
|
|
thumb2-mla.ll
|
|
|
|
thumb2-mls.ll
|
|
|
|
thumb2-mov.ll
|
|
|
|
thumb2-mul.ll
|
|
|
|
thumb2-mulhi.ll
|
|
|
|
thumb2-mvn2.ll
|
|
|
|
thumb2-mvn.ll
|
|
|
|
thumb2-neg.ll
|
|
|
|
thumb2-orn2.ll
|
|
|
|
thumb2-orn.ll
|
|
|
|
thumb2-orr2.ll
|
|
|
|
thumb2-orr.ll
|
|
|
|
thumb2-pack.ll
|
|
|
|
thumb2-rev16.ll
|
|
|
|
thumb2-rev.ll
|
|
|
|
thumb2-ror.ll
|
|
|
|
thumb2-rsb2.ll
|
|
|
|
thumb2-rsb.ll
|
|
|
|
thumb2-sbc.ll
|
|
|
|
thumb2-select_xform.ll
|
|
|
|
thumb2-select.ll
|
|
|
|
thumb2-shifter.ll
|
|
|
|
thumb2-smla.ll
|
|
|
|
thumb2-smul.ll
|
|
|
|
thumb2-spill-q.ll
|
|
|
|
thumb2-str_post.ll
|
|
|
|
thumb2-str_pre.ll
|
|
|
|
thumb2-str.ll
|
|
|
|
thumb2-strb.ll
|
|
|
|
thumb2-strh.ll
|
|
|
|
thumb2-sub2.ll
|
|
|
|
thumb2-sub3.ll
|
|
|
|
thumb2-sub4.ll
|
|
|
|
thumb2-sub5.ll
|
|
|
|
thumb2-sub.ll
|
|
|
|
thumb2-sxt_rot.ll
|
|
|
|
thumb2-sxt-uxt.ll
|
|
|
|
thumb2-tbb.ll
|
|
|
|
thumb2-tbh.ll
|
|
|
|
thumb2-teq2.ll
|
|
|
|
thumb2-teq.ll
|
|
|
|
thumb2-tst2.ll
|
|
|
|
thumb2-tst.ll
|
|
|
|
thumb2-uxt_rot.ll
|
|
|
|
thumb2-uxtb.ll
|
|
|
|
tls1.ll
|
[test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:47:16 -08:00 |
|
tls2.ll
|
|
|
|
tpsoft.ll
|
[SimplifyCFG] Tail-merging all blocks with ret terminator
|
2021-06-24 13:15:39 +03:00 |
|
umulo-64-legalisation-lowering.ll
|
|
|
|
umulo-128-legalisation-lowering.ll
|
Do not generate calls to the 128-bit function __multi3() on 32-bit ARM
|
2021-06-11 11:45:21 +01:00 |
|
unreachable-large-offset-gep.ll
|
|
|
|
urem-seteq-illegal-types.ll
|
Support {S,U}REMEqFold before legalization
|
2021-04-01 01:35:41 +03:00 |
|
v8_deprecate_IT.ll
|
|
|
|
v8_IT_1.ll
|
|
|
|
v8_IT_2.ll
|
|
|
|
v8_IT_3.ll
|
|
|
|
v8_IT_4.ll
|
[SimplifyCFG] Tail-merging all blocks with ret terminator
|
2021-06-24 13:15:39 +03:00 |
|
v8_IT_5.ll
|
|
|
|
v8_IT_6.ll
|
|
|
|
vmovdrroffset.ll
|
|
|
|
vqabs.ll
|
|
|
|
vqneg.ll
|
|
|
