mirror of
https://github.com/RPCS3/llvm-mirror.git
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b47792a75b
Debug info is currently preventing VPT block creation, leading to different codegen. This patch attempts to skip any debug instructions during vpt block creation, making sure they do not interfere. Differential Revision: https://reviews.llvm.org/D103610
111 lines
7.1 KiB
YAML
111 lines
7.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-none-unknown-eabihf"
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define <4 x i32> @test(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) #0 !dbg !5 {
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entry:
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call void @llvm.dbg.value(metadata <4 x i32> %x, metadata !17, metadata !DIExpression()), !dbg !21
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call void @llvm.dbg.value(metadata <4 x i32> %y, metadata !18, metadata !DIExpression()), !dbg !21
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call void @llvm.dbg.value(metadata <4 x i32> %z, metadata !19, metadata !DIExpression()), !dbg !21
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%0 = icmp sle <4 x i32> %x, %y, !dbg !22
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call void @llvm.dbg.value(metadata i32 undef, metadata !20, metadata !DIExpression()), !dbg !21
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%1 = tail call <4 x i32> @llvm.arm.mve.add.predicated.v4i32.v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i1> %0, <4 x i32> %z), !dbg !23
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call void @llvm.dbg.value(metadata <4 x i32> %1, metadata !19, metadata !DIExpression()), !dbg !21
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%2 = icmp sgt <4 x i32> %x, %y, !dbg !24
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call void @llvm.dbg.value(metadata i32 undef, metadata !20, metadata !DIExpression()), !dbg !21
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%3 = tail call <4 x i32> @llvm.arm.mve.add.predicated.v4i32.v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i1> %2, <4 x i32> %1), !dbg !25
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call void @llvm.dbg.value(metadata <4 x i32> %3, metadata !19, metadata !DIExpression()), !dbg !21
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ret <4 x i32> %3, !dbg !26
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}
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declare <4 x i32> @llvm.arm.mve.add.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
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declare void @llvm.dbg.value(metadata, metadata, metadata) #2
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attributes #0 = { "target-features"="+fullfp16,+lob,+mve.fp" }
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attributes #1 = { nounwind readnone "target-features"="+fullfp16,+lob,+mve.fp" }
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attributes #2 = { nofree nosync nounwind readnone speculatable willreturn "target-features"="+fullfp16,+lob,+mve.fp" }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3, !4}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 13.0.0 (https://github.com/llvm/llvm-project 921572a18dc9b97c259bda2ce8130f04b2ebe3ed)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
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!1 = !DIFile(filename: "tmp.c", directory: "/work/llvm-project/build")
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!2 = !{}
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!3 = !{i32 7, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 2, type: !6, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16)
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!6 = !DISubroutineType(types: !7)
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!7 = !{!8, !8, !8, !8}
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!8 = !DIDerivedType(tag: DW_TAG_typedef, name: "int32x4_t", file: !9, line: 28, baseType: !10)
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!9 = !DIFile(filename: "lib/clang/13.0.0/include/arm_mve.h", directory: "/work/llvm-project/build")
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!10 = !DICompositeType(tag: DW_TAG_array_type, baseType: !11, size: 128, flags: DIFlagVector, elements: !14)
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!11 = !DIDerivedType(tag: DW_TAG_typedef, name: "int32_t", file: !12, line: 58, baseType: !13)
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!12 = !DIFile(filename: "pb-rel/testabletools/include/stdint.h", directory: "/work")
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!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
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!14 = !{!15}
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!15 = !DISubrange(count: 4)
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!16 = !{!17, !18, !19, !20}
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!17 = !DILocalVariable(name: "x", arg: 1, scope: !5, file: !1, line: 2, type: !8)
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!18 = !DILocalVariable(name: "y", arg: 2, scope: !5, file: !1, line: 2, type: !8)
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!19 = !DILocalVariable(name: "z", arg: 3, scope: !5, file: !1, line: 2, type: !8)
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!20 = !DILocalVariable(name: "p", scope: !5, file: !1, line: 3, type: !13)
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!21 = !DILocation(line: 0, scope: !5)
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!22 = !DILocation(line: 3, column: 11, scope: !5)
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!23 = !DILocation(line: 4, column: 7, scope: !5)
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!24 = !DILocation(line: 5, column: 7, scope: !5)
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!25 = !DILocation(line: 6, column: 7, scope: !5)
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!26 = !DILocation(line: 7, column: 3, scope: !5)
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...
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---
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name: test
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0', virtual-reg: '' }
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- { reg: '$q1', virtual-reg: '' }
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- { reg: '$q2', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: $q0, $q1, $q2
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; CHECK-LABEL: name: test
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; CHECK: liveins: $q0, $q1, $q2
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; CHECK: DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21
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; CHECK: DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21
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; CHECK: DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21
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; CHECK: DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21
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; CHECK: DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
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; CHECK: DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
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; CHECK: DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21
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; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit killed $q1, implicit killed $q0, implicit killed $q2, debug-location !23 {
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; CHECK: MVE_VPTv4s32 12, renamable $q1, renamable $q0, 10, implicit-def $vpr, debug-location !23
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; CHECK: renamable $q2 = MVE_VADDi32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q2, debug-location !23
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; CHECK: DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21
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; CHECK: DBG_VALUE internal $q2, $noreg, !19, !DIExpression(), debug-location !21
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; CHECK: renamable $q2 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 2, internal killed renamable $vpr, internal killed renamable $q2, debug-location !25
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; CHECK: DBG_VALUE internal $q2, $noreg, !19, !DIExpression(), debug-location !21
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; CHECK: }
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; CHECK: $q0 = MVE_VORR killed $q2, killed $q2, 0, $noreg, undef $q0, debug-location !26
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0, debug-location !26
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DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21
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DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21
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DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21
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DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21
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DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
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DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
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renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 10, 0, $noreg, debug-location !22
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DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21
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renamable $q2 = MVE_VADDi32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q2, debug-location !23
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DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21
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DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
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renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, debug-location !24
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renamable $q2 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q2, debug-location !25
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DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
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$q0 = MVE_VORR killed $q2, killed $q2, 0, $noreg, undef $q0, debug-location !26
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tBX_RET 14 /* CC::al */, $noreg, implicit $q0, debug-location !26
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...
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