mirror of
https://github.com/RPCS3/llvm-mirror.git
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e4ceb59da9
Summary: This fixes a case where the argument to a sendmsg intrinsic ends up in a VGPR, for whatever reason. The underlying performance issue is that a multiplication that can be an s_mul_i32 is instead needlessly generated as v_mul_u32_u24, but this is not addressed by this patch. Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328 Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45826 llvm-svn: 330393
143 lines
3.7 KiB
LLVM
143 lines
3.7 KiB
LLVM
;RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}test_interrupt:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsg sendmsg(MSG_INTERRUPT)
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define amdgpu_kernel void @test_interrupt() {
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body:
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call void @llvm.amdgcn.s.sendmsg(i32 1, i32 0);
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ret void
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}
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; GCN-LABEL: {{^}}test_gs_emit:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 0)
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define amdgpu_kernel void @test_gs_emit() {
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body:
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call void @llvm.amdgcn.s.sendmsg(i32 34, i32 0);
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ret void
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}
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; GCN-LABEL: {{^}}test_gs_cut:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 1)
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define amdgpu_kernel void @test_gs_cut() {
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body:
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call void @llvm.amdgcn.s.sendmsg(i32 274, i32 0);
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ret void
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}
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; GCN-LABEL: {{^}}test_gs_emit_cut:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2)
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define amdgpu_kernel void @test_gs_emit_cut() {
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body:
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call void @llvm.amdgcn.s.sendmsg(i32 562, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}test_gs_done:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)
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define amdgpu_kernel void @test_gs_done() {
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body:
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call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}sendmsg:
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; GCN: s_mov_b32 m0, s0
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; VI-NEXT: s_nop 0
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; GCN-NEXT: sendmsg(MSG_GS_DONE, GS_OP_NOP)
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; GCN-NEXT: s_endpgm
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define amdgpu_gs void @sendmsg(i32 inreg %a) #0 {
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call void @llvm.amdgcn.s.sendmsg(i32 3, i32 %a)
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ret void
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}
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; GCN-LABEL: {{^}}sendmsghalt:
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; GCN: s_mov_b32 m0, s0
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; VI-NEXT: s_nop 0
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; GCN-NEXT: s_sendmsghalt sendmsg(MSG_INTERRUPT)
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @sendmsghalt(i32 inreg %a) #0 {
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call void @llvm.amdgcn.s.sendmsghalt(i32 1, i32 %a)
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ret void
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}
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; GCN-LABEL: {{^}}test_interrupt_halt:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsghalt sendmsg(MSG_INTERRUPT)
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define amdgpu_kernel void @test_interrupt_halt() {
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body:
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call void @llvm.amdgcn.s.sendmsghalt(i32 1, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}test_gs_emit_halt:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_EMIT, 0)
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define amdgpu_kernel void @test_gs_emit_halt() {
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body:
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call void @llvm.amdgcn.s.sendmsghalt(i32 34, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}test_gs_cut_halt:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_CUT, 1)
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define amdgpu_kernel void @test_gs_cut_halt() {
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body:
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call void @llvm.amdgcn.s.sendmsghalt(i32 274, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}test_gs_emit_cut_halt:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2)
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define amdgpu_kernel void @test_gs_emit_cut_halt() {
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body:
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call void @llvm.amdgcn.s.sendmsghalt(i32 562, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}test_gs_done_halt:
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; GCN: s_mov_b32 m0, 0
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; GCN-NOT: s_mov_b32 m0
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; GCN: s_sendmsghalt sendmsg(MSG_GS_DONE, GS_OP_NOP)
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define amdgpu_kernel void @test_gs_done_halt() {
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body:
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call void @llvm.amdgcn.s.sendmsghalt(i32 3, i32 0)
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ret void
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}
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; TODO: This should use s_mul_i32 instead of v_mul_u32_u24 + v_readfirstlane!
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;
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; GCN-LABEL: {{^}}test_mul24:
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; GCN: v_mul_u32_u24_e32
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; GCN: v_readfirstlane_b32
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; GCN: s_mov_b32 m0,
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; GCN: s_sendmsg sendmsg(MSG_INTERRUPT)
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define amdgpu_gs void @test_mul24(i32 inreg %arg) {
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body:
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%tmp1 = and i32 %arg, 511
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%tmp2 = mul nuw nsw i32 %tmp1, 12288
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call void @llvm.amdgcn.s.sendmsg(i32 1, i32 %tmp2)
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ret void
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}
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declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0
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declare void @llvm.amdgcn.s.sendmsghalt(i32, i32) #0
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attributes #0 = { nounwind }
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