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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 04:52:54 +02:00
llvm-mirror/test/CodeGen/AMDGPU
Matt Arsenault 334df8b0bc AMDGPU: Don't use struct type for argument layout
This was introducing unnecessary padding after the explicit
arguments, depending on the alignment of the total struct type.
Also has the side effect of avoiding creating an extra GEP for
the offset from the base kernel argument to the explicit kernel
argument offset.

llvm-svn: 335999
2018-06-29 17:31:42 +00:00
..
GlobalISel AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
32-bit-local-address-space.ll
add_i64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
add_i128.ll
add-debug.ll
add.i16.ll
add.ll AMDGPU: Fix broken check lines 2018-05-29 19:35:53 +00:00
add.v2i16.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
addrspacecast-captured.ll
addrspacecast-constantexpr.ll
addrspacecast.ll
adjust-writemask-invalid-copy.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
alignbit-pat.ll
alloca.ll
always-uniform.ll
amdgcn.bitcast.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
amdgcn.private-memory.ll
amdgpu-alias-analysis.ll
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-i16-to-i32.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-codegenprepare-idiv.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-inline.ll
amdgpu-shader-calling-convention.ll
amdgpu.private-memory.ll AMDGPU: Use more custom insert/extract_vector_elt lowering 2018-06-05 19:52:46 +00:00
amdgpu.work-item-intrinsics.deprecated.ll
amdhsa-trap-num-sgprs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
amdpal_scratch_mergedshader.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
amdpal-cs.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll [AMDGPU] For OS type AMDPAL, fixed scratch on compute shader 2018-04-10 11:25:15 +00:00
and-gcn.ll
and.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
annotate-kernel-features-hsa-call.ll
annotate-kernel-features-hsa.ll
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
atomic_cmp_swap_local.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
atomic_load_add.ll
atomic_load_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomic_load_sub.ll
atomic_store_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
attr-amdgpu-flat-work-group-size.ll
attr-amdgpu-num-sgpr-spill-to-smem.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
attr-amdgpu-num-sgpr.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
basic-call-return.ll
basic-loop.ll
bfe_uint.ll
bfe-combine.ll
bfe-patterns.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
bfi_int.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
bfm.ll
big_alu.ll
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
br_cc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll
branch-relaxation.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
branch-uniformity.ll
break-smem-soft-clauses.mir
break-vmem-soft-clauses.mir
bswap.ll
buffer-schedule.ll
bug-vopc-commute.ll
build_vector.ll
byval-frame-setup.ll
call_fs.ll
call-argument-types.ll
call-encoding.ll
call-graph-register-usage.ll
call-preserved-registers.ll
call-return-types.ll AMDGPU: Fix not including v2f64 in SReg_128 2018-06-07 12:16:31 +00:00
callee-frame-setup.ll
callee-special-input-sgprs.ll
callee-special-input-vgprs.ll
calling-conventions.ll
captured-frame-index.ll
cayman-loop-bug.ll
cf_end.ll
cf-loop-on-constant.ll AMDGPU: Try a lot harder to emit scalar loads 2018-06-07 09:54:49 +00:00
cf-stack-bug.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes.ll
cgp-bitfield-extract.ll
clamp-modifier.ll [AMDGPU] Enabled v2.16 literals for VOP3P 2018-04-17 23:09:05 +00:00
clamp-omod-special-case.mir
clamp.ll
cluster-flat-loads-postra.mir
cluster-flat-loads.mir
cndmask-no-def-vcc.ll
coalescer_distribute.ll
coalescer_remat.ll
coalescer-extend-pruned-subrange.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-identical-values-undef.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-subranges-another-copymi-not-live.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-subranges-another-prune-error.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-subreg-join.mir AMDGPU: Turn D16 for MIMG instructions into a regular operand 2018-06-21 13:36:01 +00:00
coalescer-subregjoin-fullcopy.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-with-subregs-bad-identical.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescing-with-subregs-in-loop-bug.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
code-object-v3.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
codegen-prepare-addrmode-sext.ll
collapse-endcf.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
combine_vloads.ll
combine-and-sext-bool.ll
combine-cond-add-sub.ll [AMDGPU] A trivial fix for a buildbot failure caused by "commit 224a839fcbbead221f872cd32a1dd0c308d37299". 2018-05-02 18:16:39 +00:00
combine-ftrunc.ll
comdat.ll [AMDGPU] Fix compilation failure when IR contains comdat 2018-05-11 20:40:14 +00:00
commute_modifiers.ll
commute-compares.ll
commute-shifts.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
complex-folding.ll
concat_vectors.ll DAG: Fix creating concat_vectors with illegal type 2018-06-15 12:09:15 +00:00
constant-address-space-32bit.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
constant-fold-imm-immreg.mir
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556) 2018-04-25 12:32:46 +00:00
control-flow-optnone.ll
convergent-inlineasm.ll
copy-illegal-type.ll
copy-to-reg.ll
ctlz_zero_undef.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
ctlz.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
ctpop16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
ctpop64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
ctpop.ll AMDGPU: Don't use struct type for argument layout 2018-06-29 17:31:42 +00:00
cttz_zero_undef.ll
cube.ll
cvt_f32_ubyte.ll
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
dagcombine-setcc-select.ll [AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | cc 2018-06-16 03:46:59 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dead_copy.mir
debug-value2.ll [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
debug-value.ll
debug.ll
debugger-emit-prologue.ll [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
debugger-insert-nops.ll [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
default-fp-mode.ll
detect-dead-lanes.mir
disconnected-predset-break-bug.ll
diverge-extra-formal-args.ll [AMDGPU] Fix issues for backend divergence tracking 2018-04-18 13:53:31 +00:00
diverge-interp-mov-lower.ll [AMDGPU] Fix issues for backend divergence tracking 2018-04-18 13:53:31 +00:00
drop-mem-operand-move-smrd.ll
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2.ll
ds_read2st64.ll
ds_write2.ll
ds_write2st64.ll
ds-combine-large-stride.ll
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll
dynamic_stackalloc.ll
early-if-convert-cost.ll
early-if-convert.ll
early-inline-alias.ll
early-inline.ll
elf-header-flags-mach.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
elf-header-flags-xnack.ll
elf-header-osabi.ll
elf-notes.ll AMDHSA: Code object v3 updates 2018-06-12 18:02:46 +00:00
elf.ll
elf.r600.ll
else.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir
enqueue-kernel.ll [AMDGPU] Change enqueue kernel handle type 2018-06-13 17:31:51 +00:00
env-amdgiz.ll
env-amdgizcl.ll
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll AMDGPU: Custom lower v4i16/v4f16 vector operations 2018-05-16 11:47:30 +00:00
extload-private.ll
extload.ll
extract_vector_elt-f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
extract_vector_elt-f64.ll
extract_vector_elt-i8.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
extract_vector_elt-i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
extract_vector_elt-i64.ll
extract-lowbits.ll [AMDGPU] Recognize x & ~(-1 << y) pattern. 2018-06-15 09:56:45 +00:00
extract-vector-elt-build-vector-combine.ll
extractelt-to-trunc.ll
fabs.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fabs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fadd64.ll
fadd-fma-fmul-combine.ll
fadd.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fadd.ll Utilize new SDNode flag functionality to expand current support for fadd 2018-06-18 23:44:59 +00:00
fcanonicalize-elimination.ll
fcanonicalize.f16.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
fcanonicalize.ll DAG: Fix not legalizing vector fcanonicalizes 2018-04-26 19:21:37 +00:00
fceil64.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcmp.ll
fconst64.ll
fcopysign.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f32.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fdiv32-to-rcp-folding.ll [AMDGPU] Improve reciprocal handling 2018-06-06 22:22:32 +00:00
fdiv.f16.ll Utilize new SDNode flag functionality to expand current support for fdiv 2018-06-15 20:44:55 +00:00
fdiv.f64.ll
fdiv.ll
fence-amdgiz.ll
fence-barrier.ll [AMDGPU][Waitcnt] Remove obsolete waitcnt option 2018-05-25 20:24:08 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
ffloor.f64.ll
ffloor.ll
fix-vgpr-copies.mir
fix-wwm-liveness.mir
flat_atomics_i64.ll
flat_atomics.ll
flat-address-space.ll
flat-for-global-subtarget-feature.ll
flat-load-clustering.mir
flat-scratch-reg.ll
floor.ll
fma-combine.ll
fma.f64.ll
fma.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmad.ll
fmax3.f64.ll
fmax3.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
fmax_legacy.f64.ll
fmax_legacy.ll
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll
fmed3.ll
fmin3.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
fmin_fmax_legacy.amdgcn.ll
fmin_legacy.f64.ll
fmin_legacy.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmin.ll
fminnum.f64.ll
fminnum.ll
fmul64.ll
fmul-2-combine-multi-use.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmul.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmul.ll
fmuladd.f16.ll
fmuladd.f32.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
fmuladd.f64.ll
fmuladd.v2f16.ll [AMDGPU] Enabled v2.16 literals for VOP3P 2018-04-17 23:09:05 +00:00
fnearbyint.ll
fneg-combines.ll
fneg-fabs.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg-fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg-fabs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg.f16.ll AMDGPU: Use scalar operations for f16 fabs/fneg patterns 2018-06-07 10:15:20 +00:00
fneg.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg.ll
fold-cndmask.mir
fold-fmul-to-neg-abs.ll
fold-imm-f16-f32.mir
fold-immediate-output-mods.mir
fold-implicit-operand.mir
fold-multiple.mir
fold-operands-order.mir
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll
fp_to_uint.f64.ll
fp_to_uint.ll
fp-classify.ll
fpext-free.ll
fpext.f16.ll
fpext.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-amdgiz.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
frame-index-elimination.ll
frem.ll
fsqrt.f64.ll
fsqrt.ll
fsub64.ll
fsub.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fsub.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
function-returns.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
gep-address-space.ll
global_atomics_i64.ll
global_atomics.ll
global_smrd_cfg.ll
global_smrd.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
global-constant.ll
global-directive.ll
global-extload-i16.ll
global-smrd-unknown.ll AMDGPU: Don't use undef in a test 2018-05-08 18:43:34 +00:00
global-variable-relocs.ll
gv-const-addrspace.ll
gv-offset-folding.ll
half.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
hazard-inlineasm.mir
hazard.mir
hoist-cond.ll
hsa-default-device.ll
hsa-fp-mode.ll
hsa-func-align.ll
hsa-func.ll
hsa-globals.ll
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg.ll
hsa-metadata-enqueu-kernel.ll AMDGPU/Metadata: Always report a fixed number of hidden arguments 2018-04-05 20:46:04 +00:00
hsa-metadata-from-llvm-ir-full.ll AMDGPU: Respect align argument parameter 2018-06-25 14:29:04 +00:00
hsa-metadata-hidden-args.ll AMDGPU/Metadata: Always report a fixed number of hidden arguments 2018-04-05 20:46:04 +00:00
hsa-metadata-images.ll
hsa-metadata-invalid-ocl-version-1.ll
hsa-metadata-invalid-ocl-version-2.ll
hsa-metadata-invalid-ocl-version-3.ll
hsa-metadata-kernel-code-props.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
hsa-metadata-kernel-debug-props.ll AMDGPU: Remove ability to reserve VGPRs for debugger 2018-06-21 20:28:19 +00:00
hsa-note-no-func.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
hsa.ll
huge-private-buffer.ll
i1-copy-from-loop.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
i1-copy-implicit-def.ll
i1-copy-phi.ll
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
idiv-licm.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
illegal-sgpr-to-vgpr-copy.ll
image-attributes.ll
image-resource-id.ll
image-schedule.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
imm16.ll AMDGPU: Try a lot harder to emit scalar loads 2018-06-07 09:54:49 +00:00
imm.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
immv216.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
indirect-addressing-si-noopt.ll
indirect-addressing-si.ll
indirect-private-64.ll
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
inline-asm.ll
inline-attr.ll
inline-calls.ll
inline-constraints.ll [AMDGPU] Inline asm - added i16, half and i128 types support 2018-06-08 16:29:04 +00:00
inlineasm-16.ll [AMDGPU] Inline asm - added i16, half and i128 types support 2018-06-08 16:29:04 +00:00
inlineasm-illegal-type.ll [AMDGPU] Inline asm - added i16, half and i128 types support 2018-06-08 16:29:04 +00:00
inlineasm-packed.ll
InlineAsmCrash.ll
input-mods.ll
insert_subreg.ll
insert_vector_elt.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
insert_vector_elt.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
insert-skips-kill-uncond.mir AMDGPU: Add implicit def of SCC to kill and indirect pseudos 2018-06-21 13:36:08 +00:00
insert-waitcnts-callee.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
insert-waitcnts-exp.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
inserted-wait-states.mir [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
internalize.ll
invalid-addrspacecast.ll
invalid-alloca.ll
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir
ipra.ll
jump-address.ll
kcache-fold.ll
kernarg-stack-alignment.ll
kernel-args.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
knownbits-recursion.ll
large-alloca-compute.ll
large-alloca-graphics.ll
large-constant-initializer.ll
large-work-group-promote-alloca.ll
lds_atomic_f32.ll
lds-alignment.ll
lds-global-non-entry-func.ll AMDGPU: Error on LDS global address in functions 2018-06-08 08:05:54 +00:00
lds-initializer.ll
lds-m0-init-in-loop.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
lds-zero-initializer.ll
legalize-fp-load-invariant.ll DAG: Stop dropping invariant/dereferencable 2018-06-05 14:52:24 +00:00
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
lit.local.cfg
literals.ll
liveness.mir
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll
llvm.amdgcn.atomic.inc.ll
llvm.amdgcn.buffer.atomic.ll
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
llvm.amdgcn.buffer.store.format.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.buffer.store.format.ll [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account. 2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.store.ll [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account. 2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.class.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pk.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pkrtz.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
llvm.amdgcn.div.fixup.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.fixup.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.fmas.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.scale.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
llvm.amdgcn.fmad.ftz.f16.ll [AMDGPU] Overload llvm.amdgcn.fmad.ftz to support f16 2018-06-28 15:24:46 +00:00
llvm.amdgcn.fmad.ftz.ll [AMDGPU] Overload llvm.amdgcn.fmad.ftz to support f16 2018-06-28 15:24:46 +00:00
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.atomic.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.d16.dim.ll AMDGPU: Dimension-aware image intrinsics 2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll AMDGPU: Dimension-aware image intrinsics 2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.gather4.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.gather4.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.getlod.dim.ll AMDGPU: Select MIMG instructions manually in SITargetLowering 2018-06-21 13:36:57 +00:00
llvm.amdgcn.image.sample.d16.dim.ll AMDGPU: Dimension-aware image intrinsics 2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.sample.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.sample.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll AMDGPU: Don't use struct type for argument layout 2018-06-29 17:31:42 +00:00
llvm.amdgcn.init.exec.ll AMDGPU: Fix a corner case crash in SIOptimizeExecMasking 2018-04-23 13:05:50 +00:00
llvm.amdgcn.interp.ll
llvm.amdgcn.kernarg.segment.ptr.ll AMDGPU: Round up kernel argument allocation size 2018-05-29 19:35:00 +00:00
llvm.amdgcn.kill.ll AMDGPU: Add implicit def of SCC to kill and indirect pseudos 2018-06-21 13:36:08 +00:00
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.ps.live.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
llvm.amdgcn.sdot4.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
llvm.amdgcn.sdot8.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
llvm.amdgcn.sendmsg.ll AMDGPU: Legalize the operand of SI_INIT_M0 2018-04-20 07:14:25 +00:00
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.tbuffer.store.ll [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account. 2018-04-26 16:11:19 +00:00
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
llvm.amdgcn.udot4.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
llvm.amdgcn.udot8.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.workgroup.id.ll
llvm.amdgcn.workitem.id.ll
llvm.amdgcn.wqm.vote.ll
llvm.amdgcn.writelane.ll
llvm.AMDGPU.kill.ll
llvm.ceil.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.cos.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.cos.ll
llvm.dbg.value.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.fma.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.fmuladd.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll
llvm.log10.ll
llvm.log.f16.ll
llvm.log.ll
llvm.maxnum.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.memcpy.ll
llvm.minnum.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.SI.load.dword.ll
llvm.SI.tbuffer.store.ll
llvm.sin.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i8.ll
load-constant-i16.ll
load-constant-i32.ll
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
load-global-i64.ll
load-hi16.ll AMDGPU: Add D16 instructions preserve unused bits feature 2018-05-04 20:06:57 +00:00
load-input-fold.ll
load-lo16.ll
load-local-f32-no-ds128.ll AMDGPU: Add a missing test for the 128-bit local addr space option 2018-05-15 21:41:57 +00:00
load-local-f32.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-f64.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-i1.ll
load-local-i8.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-i16.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-i32.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-i64.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-private-double16-amdgiz.ll
load-select-ptr.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-weird-sizes.ll
local-64.ll
local-atomics64.ll
local-atomics.ll
local-memory.amdgcn.ll
local-memory.ll
local-memory.r600.ll
local-stack-slot-offset.ll
loop_break.ll
loop_exit_with_xor.ll [AMDGPU] Fixed incorrect break from loop 2018-05-25 07:55:04 +00:00
loop-address.ll
loop-idiom.ll
lower-kernargs.ll AMDGPU: Don't use struct type for argument layout 2018-06-29 17:31:42 +00:00
lower-mem-intrinsics.ll
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll
lshr.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll
mad-combine.ll
mad-mix-hi.ll
mad-mix-lo.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
mad-mix.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
madak.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
madmk.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
max3.ll
max-literals.ll
max.i16.ll
max.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mem-builtins.ll
memory_clause.ll [AMDGPU] Construct memory clauses before RA 2018-05-31 20:13:51 +00:00
memory_clause.mir AMDGPU: Turn D16 for MIMG instructions into a regular operand 2018-06-21 13:36:01 +00:00
memory-legalizer-atomic-cmpxchg.ll
memory-legalizer-atomic-fence.ll
memory-legalizer-atomic-insert-end.mir
memory-legalizer-atomic-rmw.ll
memory-legalizer-invalid-addrspace.mir [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-invalid-syncscope.ll [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-load.ll [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-local.mir [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-multiple-mem-operands-atomics.mir [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
memory-legalizer-region.mir [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-store-infinite-loop.ll
memory-legalizer-store.ll
merge-load-store-physreg.mir
merge-load-store-vreg.mir
merge-load-store.mir
merge-m0.mir
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
mesa_regression.ll
min3.ll
min.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
misched-killflags.mir
missing-store.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
move-addr64-rsrc-dead-subreg-writes.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
mul_int24.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul_uint24-amdgcn.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul_uint24-r600.ll
mul.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
multi-divergent-exit-region.ll AMDGPU: Don't use struct type for argument layout 2018-06-29 17:31:42 +00:00
multilevel-break.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
nested-calls.ll
nested-loop-conditions.ll Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred. 2018-06-20 22:01:04 +00:00
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-shrink-extloads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
nop-data.ll
not-scalarize-volatile-load.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
nullptr.ll
omod.ll
opencl-image-metadata.ll
operand-folding.ll
operand-spacing.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
opt-sgpr-to-vgpr-copy.mir
optimize-if-exec-masking.mir
or.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
over-max-lds-size.ll
pack.v2f16.ll
pack.v2i16.ll
packed-op-sel.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
partial-shift-shrink.ll AMDGPU: Handle partial shift reduction for variable shifts 2018-05-09 20:52:54 +00:00
partially-dead-super-register-immediate.ll
perfhint.ll [AMDGPU] Do not consider indirect acces through phi for wave limiter 2018-06-11 16:50:49 +00:00
permute.ll [AMDGPU] Corrected computeKnownBits for V_PERM_B32 2018-06-13 18:52:54 +00:00
pk_max_f16_literal.ll [AMDGPU] Truncate packed inline constant 2018-04-24 18:17:55 +00:00
postra-norename.mir
predicate-dp4.ll
predicates.ll
print-mir-custom-pseudo.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll Rename invariant.group.barrier to launder.invariant.group 2018-05-03 11:03:01 +00:00
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
promote-alloca-padding-size-estimate.ll
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-volatile.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll
r600.func-alignment.ll AMDGPU/R600: Make sure functions are cacheline aligned 2018-05-31 04:08:08 +00:00
r600.global_atomics.ll
r600.private-memory.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp_iflag.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
rcp-pattern.ll
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll
readlane_exec0.mir
README
reduce-build-vec-ext-to-ext-build-vec.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
reduction.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
reg-coalescer-sched-crash.ll
regcoal-subrange-join-seg.mir Shrink interval after moving copy in removePartialRedundancy 2018-06-18 17:16:39 +00:00
regcoal-subrange-join.mir
regcoalesce-dbg.mir [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
regcoalesce-prune.mir
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
reorder-stores.ll
reqd-work-group-size.ll AMDGPU: Add pass to optimize reqd_work_group_size 2018-05-18 21:35:00 +00:00
ret_jump.ll
ret.ll
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_addk_i32.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
saddo.ll
salu-to-valu.ll
sampler-resource-id.ll
scalar_to_vector.ll AMDGPU: Fix scalar_to_vector for v4i16/v4f16 2018-06-20 19:45:48 +00:00
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
sched-crash-dbg-value.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit2.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit3.ll [AMDGPU] Fix amdgpu-waves-per-eu accounting in scheduler 2018-05-12 01:41:56 +00:00
schedule-regpressure-limit.ll
schedule-regpressure.mir
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll
sdiv.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
sdivrem24.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
sdivrem64.ll
sdwa-gfx9.mir
sdwa-peephole-instr.mir
sdwa-peephole.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
sdwa-preserve.mir
sdwa-scalar-ops.mir
sdwa-vop2-64bit.mir
select64.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
select-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
select-opt.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
select-vectors.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
select.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
selected-stack-object.ll
sendmsg-m0-hazard.mir
set-dx10.ll
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-opt.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
setcc-sext.ll
setcc.ll
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll AMDGPU: Try a lot harder to emit scalar loads 2018-06-07 09:54:49 +00:00
sgpr-control-flow.ll AMDGPU: Don't use struct type for argument layout 2018-06-29 17:31:42 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
sgpr-spill-wrong-stack-id.mir StackSlotColoring: Decide colors per stack ID 2018-06-25 16:05:55 +00:00
sgprcopies.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shl_add_constant.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
shl_add_ptr.ll
shl-add-to-add-shl.ll
shl.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
shl.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
shrink-add-sub-constant.ll
shrink-carry.mir
shrink-vop3-carry-out.mir
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
si-annotate-cfg-loop-assert.ll
si-fix-sgpr-copies.mir
si-instr-info-correct-implicit-operands.ll
si-lower-control-flow-kill.ll AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic 2018-04-24 21:37:57 +00:00
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir [AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"' 2018-06-12 00:41:26 +00:00
si-scheduler.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
si-sgpr-spill.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
si-spill-cf.ll
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll
si-vector-hang.ll
sibling-call.ll
sign_extend.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
simplify-libcalls.ll
simplifydemandedbits-recursion.ll
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll
skip-if-dead.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
smed3.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
sminmax.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
sminmax.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
smrd-vccz-bug.ll
smrd.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
sopk-compares.ll
spill-alloc-sgpr-init-bug.ll
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll AMDGPU: Move a flawed assert when spilling SGPRs 2018-04-23 16:13:30 +00:00
spill-empty-live-interval.mir
spill-m0.ll [AMDGPU] Don't force WQM for DS op 2018-05-07 13:21:26 +00:00
spill-scavenge-offset.ll
spill-to-smem-m0.ll
spill-wide-sgpr.ll
split-scalar-i64-add.ll
split-smrd.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
split-vector-memoperand-offsets.ll
splitkit.mir
sra.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
srem.ll
srl.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
ssubo.ll
stack-realign.ll
stack-size-overflow.ll
stack-slot-color-sgpr-vgpr-spills.mir
store_typed.ll
store-barrier.ll
store-global.ll
store-hi16.ll AMDGPU: Add D16 instructions preserve unused bits feature 2018-05-04 20:06:57 +00:00
store-local.ll
store-private.ll
store-v3i64.ll
store-vector-ptrs.ll
store-weird-sizes.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
stress-calls.ll
structurize1.ll
structurize.ll
sub.i16.ll
sub.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
sub.v2i16.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
subreg_interference.mir
subreg-coalescer-crash.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
subreg-coalescer-undef-use.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir Account for undef values from predecessors in extendSegmentsToUses 2018-06-26 14:37:16 +00:00
swizzle-export.ll
syncscopes.ll
tail-call-cgp.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
trap.ll AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as 2018-05-29 19:09:13 +00:00
trunc-bitcast-vector.ll AMDGPU: Fix broken check lines in test 2018-05-08 18:43:44 +00:00
trunc-cmp-constant.ll
trunc-combine.ll AMDGPU: Add combine for trunc of bitcast from build_vector 2018-05-09 18:37:39 +00:00
trunc-store-f64-to-f16.ll
trunc-store-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
trunc-store.ll
trunc-vector-store-assertion-failure.ll
trunc.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
tti-unroll-prefs.ll
twoaddr-mad.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
uaddo.ll
udiv.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
udivrem24.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
udivrem64.ll
udivrem.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
uint_to_fp.f64.ll
uint_to_fp.i64.ll
uint_to_fp.ll
uitofp.f16.ll
umed3.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
unaligned-load-store.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
undefined-physreg-sgpr-spill.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
undefined-subreg-liverange.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
uniform-crash.ll
uniform-loop-inside-nonuniform.ll [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556) 2018-04-25 12:32:46 +00:00
unify-metadata.ll
unigine-liveness-crash.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
unknown-processor.ll
unpack-half.ll
unroll.ll
unsupported-calls.ll AMDGPU: Error on calls from graphics shaders 2018-06-28 10:18:36 +00:00
unsupported-cc.ll
urem.ll
use-sgpr-multiple-times.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
usubo.ll
v1i64-kernel-arg.ll
v_cndmask.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
v_cvt_pk_u8_f32.ll
v_mac_f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
v_mac.ll
v_madak_f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
valu-i1.ll AMDGPU: Don't use struct type for argument layout 2018-06-29 17:31:42 +00:00
vccz-corrupt-bug-workaround.mir [AMDGPU][Waitcnt] Remove the old waitcnt pass 2018-05-07 14:43:28 +00:00
vector-alloca-addrspacecast.ll AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction. 2018-05-11 22:17:57 +00:00
vector-alloca-atomic.ll AMDGPU/SI: Don't promote alloca to vector for atomic load/store 2018-05-17 21:49:44 +00:00
vector-alloca.ll
vector-extract-insert.ll
vector-legalizer-divergence.ll [CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands 2018-06-04 20:19:45 +00:00
vectorize-global-local.ll
vertex-fetch-encoding.ll
vgpr-spill-emergency-stack-slot-compute.ll
vgpr-spill-emergency-stack-slot.ll
vi-removed-intrinsics.ll
vop-shrink-frame-index.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
waitcnt-back-edge-loop.mir [AMDGPU][Waitcnt] Fix handling of loops with many bottom blocks 2018-05-30 15:47:45 +00:00
waitcnt-debug.mir [AMDGPU] Waitcnt pass: add debug options 2018-04-25 19:21:26 +00:00
waitcnt-flat.ll
waitcnt-loop-single-basic-block.mir
waitcnt-looptest.ll
waitcnt-no-redundant.mir
waitcnt-permute.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
waitcnt.mir [AMDGPU][Waitcnt] Fix handling of flat instrs 2018-06-04 16:51:59 +00:00
wave_dispatch_regs.ll [AMDGPU] Ensure there are enough registers for wave dispatch 2018-04-11 17:18:36 +00:00
widen_extending_scalar_loads.ll AMDGPU: Preserve metadata when widening loads 2018-06-05 19:52:56 +00:00
widen-smrd-loads.ll AMDGPU: Try a lot harder to emit scalar loads 2018-06-07 09:54:49 +00:00
widen-vselect-and-mask.ll
wqm.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
wqm.mir
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
xfail.r600.bitcast.ll
xnor.ll [AMDGPU] Fixed incorrect -mcpu=gfx800 in xnor.ll test. NFC. 2018-05-31 19:39:54 +00:00
xor.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
zero_extend.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
zext-i64-bit-operand.ll
zext-lid.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.