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c580e79901
When adding operands to machine instructions in case of RegisterSDNodes, generate a COPY node in case the register class does not match the one in the instruction definition. Differental Revision: https://reviews.llvm.org/D35561 llvm-svn: 324733
97 lines
3.0 KiB
LLVM
97 lines
3.0 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | \
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; RUN: FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}tgid_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW T1.X
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define amdgpu_kernel void @tgid_x(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tgid_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
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; EG: MOV [[REG]].X, T1.Y
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define amdgpu_kernel void @tgid_y(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tgid_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
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; EG: MOV [[REG]].X, T1.Z
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define amdgpu_kernel void @tgid_z(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tidig_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW T0.X
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define amdgpu_kernel void @tidig_x(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tidig_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
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; EG: MOV [[REG]].X, T0.Y
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define amdgpu_kernel void @tidig_y(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tidig_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
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; EG: MOV [[REG]].X, T0.Z
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define amdgpu_kernel void @tidig_z(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_implicit:
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; 36 prepended implicit bytes + 4(out pointer) + 4*4 = 56
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; EG: VTX_READ_32 {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}}, 56
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define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
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%implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr()
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%header.ptr = bitcast i8 addrspace(7)* %implicitarg.ptr to i32 addrspace(7)*
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%gep = getelementptr i32, i32 addrspace(7)* %header.ptr, i32 4
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%value = load i32, i32 addrspace(7)* %gep
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_implicit_dyn:
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; 36 prepended implicit bytes + 8(out pointer + in) = 44
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; EG: VTX_READ_32 {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}}, 44
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define amdgpu_kernel void @test_implicit_dyn(i32 addrspace(1)* %out, i32 %in) #1 {
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%implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr()
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%header.ptr = bitcast i8 addrspace(7)* %implicitarg.ptr to i32 addrspace(7)*
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%gep = getelementptr i32, i32 addrspace(7)* %header.ptr, i32 %in
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%value = load i32, i32 addrspace(7)* %gep
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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declare i8 addrspace(7)* @llvm.r600.implicitarg.ptr() #0
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declare i32 @llvm.r600.read.tgid.x() #0
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declare i32 @llvm.r600.read.tgid.y() #0
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declare i32 @llvm.r600.read.tgid.z() #0
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declare i32 @llvm.r600.read.tidig.x() #0
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declare i32 @llvm.r600.read.tidig.y() #0
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declare i32 @llvm.r600.read.tidig.z() #0
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attributes #0 = { readnone }
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