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ee27f88e14
This usually results in better code. Fixes using inline asm with short2, and also fixes having a different ABI for function parameters between VI and gfx9. Partially cleans up the mess used for lowering of the d16 operations. Making v4f16 legal will help clean this up more, but this requires additional work. llvm-svn: 332953
281 lines
13 KiB
LLVM
281 lines
13 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX89,GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,GFX89,GCN %s
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_v2i16:
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; GFX89: {{flat|global}}_load_dword
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; GFX89: {{flat|global}}_load_dword
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; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI-DAG: v_sub_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI-DAG: v_sub_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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define amdgpu_kernel void @v_test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
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%add = sub <2 x i16> %a, %b
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_sub_v2i16:
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; GFX9: s_load_dword [[VAL0:s[0-9]+]]
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; GFX9: s_load_dword [[VAL1:s[0-9]+]]
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; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]]
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; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]]
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; VI: s_sub_i32
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; VI: s_sub_i32
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define amdgpu_kernel void @s_test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in0, <2 x i16> addrspace(4)* %in1) #1 {
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%a = load <2 x i16>, <2 x i16> addrspace(4)* %in0
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%b = load <2 x i16>, <2 x i16> addrspace(4)* %in1
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%add = sub <2 x i16> %a, %b
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_sub_self_v2i16:
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; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]]
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; GCN: buffer_store_dword [[ZERO]]
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define amdgpu_kernel void @s_test_sub_self_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in0) #1 {
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%a = load <2 x i16>, <2 x i16> addrspace(4)* %in0
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%add = sub <2 x i16> %a, %a
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; FIXME: VI should not scalarize arg access.
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; GCN-LABEL: {{^}}s_test_sub_v2i16_kernarg:
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; GCN: s_load_dword s
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; GCN: s_load_dword s
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; GFX9: v_pk_sub_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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; VI: s_sub_i32
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; VI: s_sub_i32
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; VI: s_lshl_b32
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; VI: s_and_b32
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define amdgpu_kernel void @s_test_sub_v2i16_kernarg(<2 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) #1 {
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%add = sub <2 x i16> %a, %b
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_test_sub_v2i16_constant:
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; GFX89-DAG: {{flat|global}}_load_dword
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; GFX9-DAG: s_mov_b32 [[CONST:s[0-9]+]], 0x1c8007b{{$}}
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; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]]
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; VI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xfffffe38
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; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0xffffff85, v{{[0-9]+}}
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; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[K]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; VI: v_or_b32
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define amdgpu_kernel void @v_test_sub_v2i16_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%add = sub <2 x i16> %a, <i16 123, i16 456>
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_v2i16_neg_constant:
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; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0xfc21fcb3{{$}}
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; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]]
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; VI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3df
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; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
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; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0x34d, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_sub_v2i16_neg_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%add = sub <2 x i16> %a, <i16 -845, i16 -991>
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_neg1:
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; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, -1 op_sel_hi:[1,0]{{$}}
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; VI-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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; VI-DAG: flat_load_dword [[LOAD:v[0-9]+]]
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; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, [[LOAD]], [[ONE]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 1, [[LOAD]]
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; VI: v_or_b32_e32
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define amdgpu_kernel void @v_test_sub_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%add = sub <2 x i16> %a, <i16 -1, i16 -1>
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_lo_zero_hi:
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; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}}
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; VI: flat_load_dword [[LOAD:v[0-9]+]]
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; VI-DAG: v_and_b32_e32 [[AND:v[0-9]+]], 0xffff0000, [[LOAD]]
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; VI-DAG: v_add_u16_e32 [[ADD:v[0-9]+]], 0xffffffe0, [[LOAD]]
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; VI: v_or_b32_e32 v{{[0-9]+}}, [[ADD]], [[AND]]
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define amdgpu_kernel void @v_test_sub_v2i16_inline_lo_zero_hi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%add = sub <2 x i16> %a, <i16 32, i16 0>
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; The high element gives fp
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; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_fp_split:
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; GFX9: s_mov_b32 [[K:s[0-9]+]], 1.0
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; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
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; VI-NOT: v_subrev_i16
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; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0xffffc080
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; VI: flat_load_dword
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; VI: v_add_u16_sdwa [[ADD:v[0-9]+]], v{{[0-9]+}}, [[K]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; VI-NOT: v_subrev_i16
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; VI: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[ADD]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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define amdgpu_kernel void @v_test_sub_v2i16_inline_fp_split(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%add = sub <2 x i16> %a, <i16 0, i16 16256>
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store <2 x i16> %add, <2 x i16> addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_v2i16_zext_to_v2i32:
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; GFX9: global_load_dword [[A:v[0-9]+]]
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; GFX9: global_load_dword [[B:v[0-9]+]]
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; GFX9: v_pk_sub_i16 [[ADD:v[0-9]+]], [[A]], [[B]]
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; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]]
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; GFX9-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]]
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; GFX9: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}}
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; VI: flat_load_dword v[[A:[0-9]+]]
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; VI: flat_load_dword v[[B:[0-9]+]]
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; VI: v_sub_u16_e32 v[[ADD_LO:[0-9]+]], v[[A]], v[[B]]
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; VI-NEXT: v_sub_u16_sdwa v[[ADD_HI:[0-9]+]], v[[A]], v[[B]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-NEXT: buffer_store_dwordx2 v{{\[}}[[ADD_LO]]:[[ADD_HI]]{{\]}}
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define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
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%add = sub <2 x i16> %a, %b
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%ext = zext <2 x i16> %add to <2 x i32>
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store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_v2i16_zext_to_v2i64:
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; GFX9: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
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; GFX9: global_load_dword [[A:v[0-9]+]]
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; GFX9: global_load_dword [[B:v[0-9]+]]
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; GFX9: v_pk_sub_i16 [[ADD:v[0-9]+]], [[A]], [[B]]
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; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]]
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; GFX9-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]]
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; GFX9: buffer_store_dwordx4
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; VI: flat_load_dword [[A:v[0-9]+]]
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; VI: flat_load_dword [[B:v[0-9]+]]
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; VI: v_sub_u16_e32 v[[ADD_LO:[0-9]+]], [[A]], [[B]]
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; VI: v_sub_u16_sdwa v[[ADD_HI:[0-9]+]], [[A]], [[B]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: buffer_store_dwordx4
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define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
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%add = sub <2 x i16> %a, %b
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%ext = zext <2 x i16> %add to <2 x i64>
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store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_v2i16_sext_to_v2i32:
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; GFX9: global_load_dword [[A:v[0-9]+]]
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; GFX9: global_load_dword [[B:v[0-9]+]]
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; GFX9: v_pk_sub_i16 [[ADD:v[0-9]+]], [[A]], [[B]]
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; GFX9-DAG: v_bfe_i32 v[[ELT0:[0-9]+]], [[ADD]], 0, 16
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; GFX9-DAG: v_ashrrev_i32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]]
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; GFX9: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}}
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; VI: flat_load_dword
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; VI: flat_load_dword
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; VI-DAG: v_sub_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-DAG: v_sub_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: buffer_store_dwordx2
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define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
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%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
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%add = sub <2 x i16> %a, %b
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%ext = sext <2 x i16> %add to <2 x i32>
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store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_v2i16_sext_to_v2i64:
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; GCN: {{flat|global}}_load_dword
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; GCN: {{flat|global}}_load_dword
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; GFX9: v_pk_sub_i16
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; GFX9: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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; VI: v_sub_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: v_sub_u16_e32
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; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
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; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
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; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
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; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
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%a = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
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%b = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
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%add = sub <2 x i16> %a, %b
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%ext = sext <2 x i16> %add to <2 x i64>
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store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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