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f58aee7cea
Summary: Also explicitly port over some tests in llvm.amdgcn.image.* that were missing. Some tests are removed because they no longer apply (i.e. explicitly testing building an address vector via insertelement). This is in preparation for the eventual removal of the old-style intrinsics. Some additional notes: - constant-address-space-32bit.ll: change some GCN-NEXT to GCN because the instruction schedule was subtly altered - insert_vector_elt.ll: the old test didn't actually test anything, because %tmp1 was not used; remove the load, because it doesn't work (Because of the amdgpu_ps calling convention? In any case, it's orthogonal to what the test claims to be testing.) Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf Reviewers: arsenm, rampitec Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D48018 llvm-svn: 335229
90 lines
3.0 KiB
LLVM
90 lines
3.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; We may have subregister live ranges that are undefined on some paths. The
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; verifier should not complain about this.
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; CHECK-LABEL: {{^}}func:
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define amdgpu_kernel void @func() #0 {
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B0:
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br i1 undef, label %B1, label %B2
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B1:
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br label %B2
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B2:
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%v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float undef>, %B0 ]
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br i1 undef, label %B30.1, label %B30.2
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B30.1:
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%sub = fsub <4 x float> %v0, undef
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br label %B30.2
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B30.2:
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%v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v0, %B2 ]
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%ve0 = extractelement <4 x float> %v3, i32 0
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store float %ve0, float addrspace(3)* undef, align 4
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ret void
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}
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; FIXME: Extra undef subregister copy should be removed before
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; overwritten with defined copy
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; CHECK-LABEL: {{^}}valley_partially_undef_copy:
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define amdgpu_ps float @valley_partially_undef_copy() #0 {
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bb:
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%tmp = load volatile i32, i32 addrspace(1)* undef, align 4
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%tmp1 = load volatile i32, i32 addrspace(1)* undef, align 4
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%tmp2 = insertelement <4 x i32> undef, i32 %tmp1, i32 0
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%tmp3 = bitcast i32 %tmp1 to float
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%tmp4 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp3, float %tmp3, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp5 = extractelement <4 x float> %tmp4, i32 0
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%tmp6 = fmul float %tmp5, undef
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%tmp7 = fadd float %tmp6, %tmp6
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%tmp8 = insertelement <4 x i32> %tmp2, i32 %tmp, i32 1
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store <4 x i32> %tmp8, <4 x i32> addrspace(1)* undef, align 16
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store float %tmp7, float addrspace(1)* undef, align 4
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br label %bb9
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bb9: ; preds = %bb9, %bb
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%tmp10 = icmp eq i32 %tmp, 0
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br i1 %tmp10, label %bb9, label %bb11
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bb11: ; preds = %bb9
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store <4 x i32> %tmp2, <4 x i32> addrspace(1)* undef, align 16
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ret float undef
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}
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; FIXME: Should be able to remove the undef copies
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; CHECK-LABEL: {{^}}partially_undef_copy:
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; CHECK: v_mov_b32_e32 v5, 5
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; CHECK: v_mov_b32_e32 v6, 6
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; CHECK: v_mov_b32_e32 v[[OUTPUT_LO:[0-9]+]], v5
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; Undef copy
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; CHECK: v_mov_b32_e32 v1, v6
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; undef copy
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; CHECK: v_mov_b32_e32 v2, v7
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; CHECK: v_mov_b32_e32 v[[OUTPUT_HI:[0-9]+]], v8
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; CHECK: v_mov_b32_e32 v[[OUTPUT_LO]], v6
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; CHECK: buffer_store_dwordx4 v{{\[}}[[OUTPUT_LO]]:[[OUTPUT_HI]]{{\]}}
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define amdgpu_kernel void @partially_undef_copy() #0 {
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%tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"()
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%tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"()
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%partially.undef.0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
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%partially.undef.1 = insertelement <4 x i32> %partially.undef.0, i32 %tmp1, i32 0
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store volatile <4 x i32> %partially.undef.1, <4 x i32> addrspace(1)* undef, align 16
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tail call void asm sideeffect "v_nop", "v={v[5:8]}"(<4 x i32> %partially.undef.0)
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ret void
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}
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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