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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
22 lines
677 B
LLVM
22 lines
677 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
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; computeKnownBits determines that we don't need a mask op that is required in the general case.
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define i8 @foo(i8 %tmp325) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: imull $111, %ecx, %eax
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; CHECK-NEXT: shrl $12, %eax
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; CHECK-NEXT: movb $37, %dl
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: mulb %dl
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; CHECK-NEXT: subb %al, %cl
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: retl
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%t546 = urem i8 %tmp325, 37
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ret i8 %t546
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}
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