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llvm-mirror/test/CodeGen/X86/verifier-phi-fail0.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

31 lines
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YAML

# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s
---
# CHECK: Bad machine code: PHI operand is not live-out from predecessor
# CHECK: - function: func0
# CHECK: - basic block: %bb.3
# CHECK: - instruction: %0:gr32 = PHI
# CHECK: - operand 1: %1
#
# CHECK: Bad machine code: PHI operand is not live-out from predecessor
# CHECK: - function: func0
# CHECK: - basic block: %bb.3
# CHECK: - instruction: %0:gr32 = PHI
# CHECK: - operand 3: %0
name: func0
tracksRegLiveness: true
body: |
bb.0:
JE_1 %bb.1, implicit undef $eflags
JMP_1 %bb.2
bb.1:
%0:gr32 = IMPLICIT_DEF
JMP_1 %bb.3
bb.2:
%1:gr32 = IMPLICIT_DEF
bb.3:
%0:gr32 = PHI %1, %bb.1, %0, %bb.2
...