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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
44 lines
963 B
YAML
44 lines
963 B
YAML
# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s
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# Check that this testcase does not crash.
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# CHECK: L4_and_memopw_io
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---
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name: fred
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tracksRegLiveness: true
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: intregs }
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- { id: 2, class: intregs }
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- { id: 3, class: intregs }
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- { id: 4, class: predregs }
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- { id: 5, class: intregs }
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- { id: 6, class: intregs }
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body: |
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bb.0:
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successors: %bb.1
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%0 = A2_tfrsi -360184608
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%1 = L2_loadri_io %0, -1024
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bb.1:
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successors: %bb.2
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%2 = A2_tfrsi -234944641
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%3 = A2_tfrsi -360185632
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L4_and_memopw_io %3, 0, %2
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bb.2:
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successors: %bb.3, %bb.4
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%4 = IMPLICIT_DEF
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J2_jumpt %4, %bb.4, implicit-def $pc
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J2_jump %bb.3, implicit-def $pc
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bb.3:
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successors: %bb.4
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bb.4:
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successors: %bb.4
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%5 = A2_tfrsi -234944521
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%6 = A2_tfrsi -360185632
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L4_and_memopw_io %6, 0, %5
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...
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