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d5effbea90
MipsSEInstrInfo class defines for internal purpose unconditional branches as Mips::B nad Mips:J even in case of microMIPS code generation. Under some conditions that leads to the bug - for rather long branch which fits to Mips jump instruction offset size, but does not fit to microMIPS jump offset size, we generate 'short' branch and later show an error 'out of range PC16 fixup' after check in the isBranchOffsetInRange routine. Differential revision: https://reviews.llvm.org/D50615 llvm-svn: 340932
99 lines
3.4 KiB
LLVM
99 lines
3.4 KiB
LLVM
; RUN: llc -march=mips -relocation-model=pic -mattr=+micromips \
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; RUN: -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
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; CHECK-LABEL: foo:
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; CHECK-NEXT: 0: 41 a2 00 00 lui $2, 0
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; CHECK-NEXT: 4: 30 42 00 00 addiu $2, $2, 0
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; CHECK-NEXT: 8: 03 22 11 50 addu $2, $2, $25
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; CHECK-NEXT: c: fc 42 00 00 lw $2, 0($2)
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; CHECK-NEXT: 10: 69 20 lw16 $2, 0($2)
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; CHECK-NEXT: 12: 40 c2 00 14 bgtz $2, 44 <foo+0x3e>
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; CHECK-NEXT: 16: 00 00 00 00 nop
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; CHECK-NEXT: 1a: 33 bd ff f8 addiu $sp, $sp, -8
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; CHECK-NEXT: 1e: fb fd 00 00 sw $ra, 0($sp)
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; CHECK-NEXT: 22: 41 a1 00 01 lui $1, 1
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; CHECK-NEXT: 26: 40 60 00 02 bal 8 <foo+0x2e>
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; CHECK-NEXT: 2a: 30 21 04 68 addiu $1, $1, 1128
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; CHECK-NEXT: 2e: 00 3f 09 50 addu $1, $ra, $1
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; CHECK-NEXT: 32: ff fd 00 00 lw $ra, 0($sp)
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; CHECK-NEXT: 36: 00 01 0f 3c jr $1
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; CHECK-NEXT: 3a: 33 bd 00 08 addiu $sp, $sp, 8
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; CHECK-NEXT: 3e: 94 00 00 02 b 8 <foo+0x46>
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; CHECK-NEXT: 42: 00 00 00 00 nop
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; CHECK-NEXT: 46: 30 20 4e 1f addiu $1, $zero, 19999
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; CHECK-NEXT: 4a: b4 22 00 14 bne $2, $1, 44 <foo+0x76>
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; CHECK-NEXT: 4e: 00 00 00 00 nop
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; CHECK-NEXT: 52: 33 bd ff f8 addiu $sp, $sp, -8
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; CHECK-NEXT: 56: fb fd 00 00 sw $ra, 0($sp)
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; CHECK-NEXT: 5a: 41 a1 00 01 lui $1, 1
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; CHECK-NEXT: 5e: 40 60 00 02 bal 8 <foo+0x66>
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; CHECK-NEXT: 62: 30 21 04 5c addiu $1, $1, 1116
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; CHECK-NEXT: 66: 00 3f 09 50 addu $1, $ra, $1
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; CHECK-NEXT: 6a: ff fd 00 00 lw $ra, 0($sp)
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; CHECK-NEXT: 6e: 00 01 0f 3c jr $1
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; CHECK-NEXT: 72: 33 bd 00 08 addiu $sp, $sp, 8
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; CHECK-NEXT: 76: 30 20 27 0f addiu $1, $zero, 9999
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; CHECK-NEXT: 7a: 94 22 00 14 beq $2, $1, 44 <foo+0xa6>
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; CHECK-NEXT: 7e: 00 00 00 00 nop
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; CHECK-NEXT: 82: 33 bd ff f8 addiu $sp, $sp, -8
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; CHECK-NEXT: 86: fb fd 00 00 sw $ra, 0($sp)
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; CHECK-NEXT: 8a: 41 a1 00 01 lui $1, 1
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; CHECK-NEXT: 8e: 40 60 00 02 bal 8 <foo+0x96>
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; CHECK-NEXT: 92: 30 21 04 2c addiu $1, $1, 1068
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; CHECK-NEXT: 96: 00 3f 09 50 addu $1, $ra, $1
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; CHECK-NEXT: 9a: ff fd 00 00 lw $ra, 0($sp)
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; CHECK-NEXT: 9e: 00 01 0f 3c jr $1
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; CHECK-NEXT: a2: 33 bd 00 08 addiu $sp, $sp, 8
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; CHECK: 10466: 00 00 00 00 nop
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; CHECK-NEXT: 1046a: 94 00 00 02 b 8 <foo+0x10472>
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; CHECK-NEXT: 1046e: 00 00 00 00 nop
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; CHECK-NEXT: 10472: 33 bd ff f8 addiu $sp, $sp, -8
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; CHECK-NEXT: 10476: fb fd 00 00 sw $ra, 0($sp)
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; CHECK-NEXT: 1047a: 41 a1 00 01 lui $1, 1
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; CHECK-NEXT: 1047e: 40 60 00 02 bal 8 <foo+0x10486>
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; CHECK-NEXT: 10482: 30 21 04 00 addiu $1, $1, 1024
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; CHECK-NEXT: 10486: 00 3f 09 50 addu $1, $ra, $1
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; CHECK-NEXT: 1048a: ff fd 00 00 lw $ra, 0($sp)
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; CHECK-NEXT: 1048e: 00 01 0f 3c jr $1
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; CHECK-NEXT: 10492: 33 bd 00 08 addiu $sp, $sp, 8
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; CHECK-NEXT: 10496: 94 00 00 02 b 8 <foo+0x1049e>
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@x = external global i32, align 4
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define void @foo() {
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%1 = load i32, i32* @x, align 4
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%2 = icmp sgt i32 %1, 0
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br i1 %2, label %la, label %lf
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la:
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switch i32 %1, label %le [
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i32 9999, label %lb
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i32 19999, label %lc
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]
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lb:
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tail call void asm sideeffect ".space 0", ""()
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br label %le
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lc:
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tail call void asm sideeffect ".space 0", ""()
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br label %le
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le:
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tail call void asm sideeffect ".space 66500", ""()
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br label %lg
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lf:
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tail call void asm sideeffect ".space 0", ""()
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br label %lg
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lg:
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tail call void asm sideeffect ".space 0", ""()
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br label %li
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li:
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tail call void asm sideeffect ".space 0", ""()
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ret void
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}
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