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llvm-mirror/test/CodeGen/SystemZ/and-xor-01.ll
Zhan Jun Liau 0606cb413f [SystemZ] Avoid generating 2 XOR instructions for (and (xor x, -1), y)
Summary:
Created a pattern to match 64-bit mode (and (xor x, -1), y)
to a shorter sequence of instructions.

Before the change, the canonical form is translated to:
        xihf    %r3, 4294967295
        xilf    %r3, 4294967295
        ngr     %r2, %r3

After the change, the canonical form is translated to:
        ngr     %r3, %r2
        xgr     %r2, %r3

Reviewers: zhanjunl, uweigand

Subscribers: llvm-commits

Author: assem

Committing on behalf of Assem.

Differential Revision: http://reviews.llvm.org/D21693

llvm-svn: 273887
2016-06-27 15:55:30 +00:00

15 lines
312 B
LLVM

; Testing peephole for generating shorter code for (and (xor b, -1), a)
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
; CHECK-LABEL: f1:
; CHECK: ngr %r3, %r2
; CHECK: xgr %r2, %r3
; CHECK: br %r14
%neg = xor i64 %b, -1
%and = and i64 %neg, %a
ret i64 %and
}