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e2588266f1
On current machines we have load-on-condition instructions that can be used to directly implement the SETCC semantics. If we have those, it is always preferable to use them instead of generating the IPM sequence. llvm-svn: 322989
441 lines
14 KiB
LLVM
441 lines
14 KiB
LLVM
; Test vector intrinsics added with z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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declare <2 x i64> @llvm.s390.vbperm(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.s390.vmslg(<2 x i64>, <2 x i64>, <16 x i8>, i32)
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declare <16 x i8> @llvm.s390.vlrl(i32, i8 *)
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declare void @llvm.s390.vstrl(<16 x i8>, i32, i8 *)
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declare {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float>, <4 x float>)
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declare {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float>, <4 x float>)
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declare {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float>, <4 x float>)
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declare {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float>, i32)
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declare <4 x float> @llvm.s390.vfisb(<4 x float>, i32, i32)
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declare <2 x double> @llvm.s390.vfmaxdb(<2 x double>, <2 x double>, i32)
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declare <2 x double> @llvm.s390.vfmindb(<2 x double>, <2 x double>, i32)
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declare <4 x float> @llvm.s390.vfmaxsb(<4 x float>, <4 x float>, i32)
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declare <4 x float> @llvm.s390.vfminsb(<4 x float>, <4 x float>, i32)
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; VBPERM.
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define <2 x i64> @test_vbperm(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_vbperm:
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; CHECK: vbperm %v24, %v24, %v26
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; CHECK: br %r14
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%res = call <2 x i64> @llvm.s390.vbperm(<16 x i8> %a, <16 x i8> %b)
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ret <2 x i64> %res
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}
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; VMSLG with no shifts.
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define <16 x i8> @test_vmslg1(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
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; CHECK-LABEL: test_vmslg1:
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; CHECK: vmslg %v24, %v24, %v26, %v28, 0
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; CHECK: br %r14
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%res = call <16 x i8> @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c, i32 0)
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ret <16 x i8> %res
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}
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; VMSLG with both shifts.
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define <16 x i8> @test_vmslg2(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
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; CHECK-LABEL: test_vmslg2:
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; CHECK: vmslg %v24, %v24, %v26, %v28, 12
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; CHECK: br %r14
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%res = call <16 x i8> @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c, i32 12)
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ret <16 x i8> %res
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}
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; VLRLR with the lowest in-range displacement.
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define <16 x i8> @test_vlrlr1(i8 *%ptr, i32 %length) {
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; CHECK-LABEL: test_vlrlr1:
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; CHECK: vlrlr %v24, %r3, 0(%r2)
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; CHECK: br %r14
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%res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr)
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ret <16 x i8> %res
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}
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; VLRLR with the highest in-range displacement.
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define <16 x i8> @test_vlrlr2(i8 *%base, i32 %length) {
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; CHECK-LABEL: test_vlrlr2:
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; CHECK: vlrlr %v24, %r3, 4095(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4095
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%res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr)
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ret <16 x i8> %res
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}
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; VLRLR with an out-of-range displacement.
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define <16 x i8> @test_vlrlr3(i8 *%base, i32 %length) {
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; CHECK-LABEL: test_vlrlr3:
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; CHECK: vlrlr %v24, %r3, 0({{%r[1-5]}})
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4096
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%res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr)
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ret <16 x i8> %res
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}
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; Check that VLRLR doesn't allow an index.
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define <16 x i8> @test_vlrlr4(i8 *%base, i64 %index, i32 %length) {
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; CHECK-LABEL: test_vlrlr4:
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; CHECK: vlrlr %v24, %r4, 0({{%r[1-5]}})
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 %index
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%res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr)
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ret <16 x i8> %res
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}
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; VLRL with the lowest in-range displacement.
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define <16 x i8> @test_vlrl1(i8 *%ptr) {
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; CHECK-LABEL: test_vlrl1:
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; CHECK: vlrl %v24, 0(%r2), 0
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; CHECK: br %r14
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%res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr)
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ret <16 x i8> %res
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}
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; VLRL with the highest in-range displacement.
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define <16 x i8> @test_vlrl2(i8 *%base) {
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; CHECK-LABEL: test_vlrl2:
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; CHECK: vlrl %v24, 4095(%r2), 0
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4095
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%res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr)
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ret <16 x i8> %res
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}
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; VLRL with an out-of-range displacement.
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define <16 x i8> @test_vlrl3(i8 *%base) {
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; CHECK-LABEL: test_vlrl3:
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; CHECK: vlrl %v24, 0({{%r[1-5]}}), 0
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4096
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%res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr)
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ret <16 x i8> %res
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}
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; Check that VLRL doesn't allow an index.
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define <16 x i8> @test_vlrl4(i8 *%base, i64 %index) {
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; CHECK-LABEL: test_vlrl4:
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; CHECK: vlrl %v24, 0({{%r[1-5]}}), 0
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 %index
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%res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr)
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ret <16 x i8> %res
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}
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; VSTRLR with the lowest in-range displacement.
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define void @test_vstrlr1(<16 x i8> %vec, i8 *%ptr, i32 %length) {
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; CHECK-LABEL: test_vstrlr1:
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; CHECK: vstrlr %v24, %r3, 0(%r2)
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; CHECK: br %r14
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call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr)
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ret void
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}
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; VSTRLR with the highest in-range displacement.
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define void @test_vstrlr2(<16 x i8> %vec, i8 *%base, i32 %length) {
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; CHECK-LABEL: test_vstrlr2:
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; CHECK: vstrlr %v24, %r3, 4095(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4095
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call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr)
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ret void
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}
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; VSTRLR with an out-of-range displacement.
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define void @test_vstrlr3(<16 x i8> %vec, i8 *%base, i32 %length) {
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; CHECK-LABEL: test_vstrlr3:
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; CHECK: vstrlr %v24, %r3, 0({{%r[1-5]}})
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4096
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call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr)
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ret void
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}
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; Check that VSTRLR doesn't allow an index.
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define void @test_vstrlr4(<16 x i8> %vec, i8 *%base, i64 %index, i32 %length) {
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; CHECK-LABEL: test_vstrlr4:
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; CHECK: vstrlr %v24, %r4, 0({{%r[1-5]}})
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 %index
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call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr)
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ret void
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}
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; VSTRL with the lowest in-range displacement.
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define void @test_vstrl1(<16 x i8> %vec, i8 *%ptr) {
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; CHECK-LABEL: test_vstrl1:
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; CHECK: vstrl %v24, 0(%r2), 8
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; CHECK: br %r14
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call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr)
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ret void
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}
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; VSTRL with the highest in-range displacement.
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define void @test_vstrl2(<16 x i8> %vec, i8 *%base) {
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; CHECK-LABEL: test_vstrl2:
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; CHECK: vstrl %v24, 4095(%r2), 8
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4095
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call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr)
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ret void
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}
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; VSTRL with an out-of-range displacement.
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define void @test_vstrl3(<16 x i8> %vec, i8 *%base) {
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; CHECK-LABEL: test_vstrl3:
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; CHECK: vstrl %v24, 0({{%r[1-5]}}), 8
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4096
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call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr)
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ret void
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}
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; Check that VSTRL doesn't allow an index.
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define void @test_vstrl4(<16 x i8> %vec, i8 *%base, i64 %index) {
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; CHECK-LABEL: test_vstrl4:
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; CHECK: vstrl %v24, 0({{%r[1-5]}}), 8
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 %index
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call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr)
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ret void
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}
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; VFCESBS with no processing of the result.
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define i32 @test_vfcesbs(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_vfcesbs:
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; CHECK: vfcesbs {{%v[0-9]+}}, %v24, %v26
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 1
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ret i32 %res
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}
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; VFCESBS, returning 1 if any elements are equal (CC != 3).
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define i32 @test_vfcesbs_any_bool(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_vfcesbs_any_bool:
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; CHECK: vfcesbs {{%v[0-9]+}}, %v24, %v26
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; CHECK: lhi %r2, 0
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; CHECK: lochile %r2, 1
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 1
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%cmp = icmp ne i32 %res, 3
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%ext = zext i1 %cmp to i32
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ret i32 %ext
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}
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; VFCESBS, storing to %ptr if any elements are equal.
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define <4 x i32> @test_vfcesbs_any_store(<4 x float> %a, <4 x float> %b,
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i32 *%ptr) {
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; CHECK-LABEL: test_vfcesbs_any_store:
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; CHECK-NOT: %r
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; CHECK: vfcesbs %v24, %v24, %v26
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; CHECK-NEXT: {{bor|bnler}} %r14
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; CHECK: mvhi 0(%r2), 0
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 0
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%cc = extractvalue {<4 x i32>, i32} %call, 1
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%cmp = icmp ule i32 %cc, 2
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br i1 %cmp, label %store, label %exit
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store:
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store i32 0, i32 *%ptr
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br label %exit
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exit:
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ret <4 x i32> %res
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}
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; VFCHSBS with no processing of the result.
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define i32 @test_vfchsbs(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_vfchsbs:
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; CHECK: vfchsbs {{%v[0-9]+}}, %v24, %v26
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 1
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ret i32 %res
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}
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; VFCHSBS, returning 1 if not all elements are higher.
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define i32 @test_vfchsbs_notall_bool(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_vfchsbs_notall_bool:
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; CHECK: vfchsbs {{%v[0-9]+}}, %v24, %v26
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; CHECK: lhi %r2, 0
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; CHECK: lochinhe %r2, 1
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 1
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%cmp = icmp sge i32 %res, 1
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%ext = zext i1 %cmp to i32
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ret i32 %ext
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}
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; VFCHSBS, storing to %ptr if not all elements are higher.
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define <4 x i32> @test_vfchsbs_notall_store(<4 x float> %a, <4 x float> %b,
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i32 *%ptr) {
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; CHECK-LABEL: test_vfchsbs_notall_store:
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; CHECK-NOT: %r
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; CHECK: vfchsbs %v24, %v24, %v26
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; CHECK-NEXT: {{bher|ber}} %r14
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; CHECK: mvhi 0(%r2), 0
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 0
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%cc = extractvalue {<4 x i32>, i32} %call, 1
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%cmp = icmp ugt i32 %cc, 0
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br i1 %cmp, label %store, label %exit
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store:
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store i32 0, i32 *%ptr
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br label %exit
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exit:
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ret <4 x i32> %res
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}
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; VFCHESBS with no processing of the result.
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define i32 @test_vfchesbs(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_vfchesbs:
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; CHECK: vfchesbs {{%v[0-9]+}}, %v24, %v26
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 1
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ret i32 %res
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}
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; VFCHESBS, returning 1 if neither element is higher or equal.
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define i32 @test_vfchesbs_none_bool(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_vfchesbs_none_bool:
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; CHECK: vfchesbs {{%v[0-9]+}}, %v24, %v26
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; CHECK: lhi %r2, 0
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; CHECK: lochio %r2, 1
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 1
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%cmp = icmp eq i32 %res, 3
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%ext = zext i1 %cmp to i32
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ret i32 %ext
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}
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; VFCHESBS, storing to %ptr if neither element is higher or equal.
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define <4 x i32> @test_vfchesbs_none_store(<4 x float> %a, <4 x float> %b,
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i32 *%ptr) {
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; CHECK-LABEL: test_vfchesbs_none_store:
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; CHECK-NOT: %r
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; CHECK: vfchesbs %v24, %v24, %v26
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; CHECK-NEXT: {{bnor|bler}} %r14
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; CHECK: mvhi 0(%r2), 0
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a,
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<4 x float> %b)
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%res = extractvalue {<4 x i32>, i32} %call, 0
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%cc = extractvalue {<4 x i32>, i32} %call, 1
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%cmp = icmp uge i32 %cc, 3
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br i1 %cmp, label %store, label %exit
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store:
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store i32 0, i32 *%ptr
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br label %exit
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exit:
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ret <4 x i32> %res
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}
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; VFTCISB with the lowest useful class selector and no processing of the result.
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define i32 @test_vftcisb(<4 x float> %a) {
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; CHECK-LABEL: test_vftcisb:
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; CHECK: vftcisb {{%v[0-9]+}}, %v24, 1
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float> %a, i32 1)
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%res = extractvalue {<4 x i32>, i32} %call, 1
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ret i32 %res
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}
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; VFTCISB with the highest useful class selector, returning 1 if all elements
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; have the right class (CC == 0).
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define i32 @test_vftcisb_all_bool(<4 x float> %a) {
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; CHECK-LABEL: test_vftcisb_all_bool:
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; CHECK: vftcisb {{%v[0-9]+}}, %v24, 4094
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; CHECK: lhi %r2, 0
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; CHECK: lochie %r2, 1
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; CHECK: br %r14
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%call = call {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float> %a, i32 4094)
|
|
%res = extractvalue {<4 x i32>, i32} %call, 1
|
|
%cmp = icmp eq i32 %res, 0
|
|
%ext = zext i1 %cmp to i32
|
|
ret i32 %ext
|
|
}
|
|
|
|
; VFISB with a rounding mode not usable via standard intrinsics.
|
|
define <4 x float> @test_vfisb_0_4(<4 x float> %a) {
|
|
; CHECK-LABEL: test_vfisb_0_4:
|
|
; CHECK: vfisb %v24, %v24, 0, 4
|
|
; CHECK: br %r14
|
|
%res = call <4 x float> @llvm.s390.vfisb(<4 x float> %a, i32 0, i32 4)
|
|
ret <4 x float> %res
|
|
}
|
|
|
|
; VFISB with IEEE-inexact exception suppressed.
|
|
define <4 x float> @test_vfisb_4_0(<4 x float> %a) {
|
|
; CHECK-LABEL: test_vfisb_4_0:
|
|
; CHECK: vfisb %v24, %v24, 4, 0
|
|
; CHECK: br %r14
|
|
%res = call <4 x float> @llvm.s390.vfisb(<4 x float> %a, i32 4, i32 0)
|
|
ret <4 x float> %res
|
|
}
|
|
|
|
; VFMAXDB.
|
|
define <2 x double> @test_vfmaxdb(<2 x double> %a, <2 x double> %b) {
|
|
; CHECK-LABEL: test_vfmaxdb:
|
|
; CHECK: vfmaxdb %v24, %v24, %v26, 4
|
|
; CHECK: br %r14
|
|
%res = call <2 x double> @llvm.s390.vfmaxdb(<2 x double> %a, <2 x double> %b, i32 4)
|
|
ret <2 x double> %res
|
|
}
|
|
|
|
; VFMINDB.
|
|
define <2 x double> @test_vfmindb(<2 x double> %a, <2 x double> %b) {
|
|
; CHECK-LABEL: test_vfmindb:
|
|
; CHECK: vfmindb %v24, %v24, %v26, 4
|
|
; CHECK: br %r14
|
|
%res = call <2 x double> @llvm.s390.vfmindb(<2 x double> %a, <2 x double> %b, i32 4)
|
|
ret <2 x double> %res
|
|
}
|
|
|
|
; VFMAXSB.
|
|
define <4 x float> @test_vfmaxsb(<4 x float> %a, <4 x float> %b) {
|
|
; CHECK-LABEL: test_vfmaxsb:
|
|
; CHECK: vfmaxsb %v24, %v24, %v26, 4
|
|
; CHECK: br %r14
|
|
%res = call <4 x float> @llvm.s390.vfmaxsb(<4 x float> %a, <4 x float> %b, i32 4)
|
|
ret <4 x float> %res
|
|
}
|
|
|
|
; VFMINSB.
|
|
define <4 x float> @test_vfminsb(<4 x float> %a, <4 x float> %b) {
|
|
; CHECK-LABEL: test_vfminsb:
|
|
; CHECK: vfminsb %v24, %v24, %v26, 4
|
|
; CHECK: br %r14
|
|
%res = call <4 x float> @llvm.s390.vfminsb(<4 x float> %a, <4 x float> %b, i32 4)
|
|
ret <4 x float> %res
|
|
}
|
|
|