RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 13:11:39 +01:00
Code Issues Projects Releases Wiki Activity
llvm-mirror/lib/Target/RISCV
History
Simon Cook 2fb7212d27 [RISCV] Add support for -ffixed-xX flags 
This adds support for reserving GPRs such that the compiler will not
choose a register for register allocation. The implementation follows
the same design as for AArch64; each reserved register becomes a target
feature and used for getting the reserved registers for a given
MachineFunction. The backend checks that it does not need to write to
any reserved register; if it does a relevant error is generated.

Differential Revision: https://reviews.llvm.org/D67185
2019-10-22 21:25:01 +01:00
..
AsmParser
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
Disassembler
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
MCTargetDesc
[RISCV] Add MachineInstr immediate verification
2019-10-16 15:06:02 +00:00
TargetInfo
Revert CMake: Make most target symbols hidden by default
2019-06-11 03:21:13 +00:00
Utils
[RISCV] Add MachineInstr immediate verification
2019-10-16 15:06:02 +00:00
CMakeLists.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
LLVMBuild.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.td
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVAsmPrinter.cpp
[RISCV] Support z and i operand modifiers
2019-07-08 05:00:26 +00:00
RISCVCallingConv.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVCallLowering.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVCallLowering.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVExpandPseudoInsts.cpp
[RISCV] Convert registers from unsigned to Register
2019-08-16 14:27:50 +00:00
RISCVFrameLowering.cpp
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVFrameLowering.h
[Alignment][NFC] Use Align for TargetFrameLowering/Subtarget
2019-10-17 07:49:39 +00:00
RISCVInstrFormats.td
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
RISCVInstrFormatsC.td
Update the file headers across all of the LLVM projects in the monorepo
2019-01-19 08:50:56 +00:00
RISCVInstrInfo.cpp
[RISCV] Add MachineInstr immediate verification
2019-10-16 15:06:02 +00:00
RISCVInstrInfo.h
[RISCV] Add MachineInstr immediate verification
2019-10-16 15:06:02 +00:00
RISCVInstrInfo.td
[RISCV] Add MachineInstr immediate verification
2019-10-16 15:06:02 +00:00
RISCVInstrInfoA.td
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
RISCVInstrInfoC.td
[RISCV] Added missing ImmLeaf predicates
2019-10-04 23:42:07 +00:00
RISCVInstrInfoD.td
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
RISCVInstrInfoF.td
[RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)
2019-10-03 15:47:28 +00:00
RISCVInstrInfoM.td
[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M
2019-01-25 05:11:34 +00:00
RISCVInstructionSelector.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Fix static analysis issues
2019-09-20 13:48:02 +00:00
RISCVISelLowering.cpp
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVISelLowering.h
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVLegalizerInfo.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVMachineFunctionInfo.h
[RISCV] Delete a ctor that is commented out. NFC
2019-07-05 08:25:14 +00:00
RISCVMCInstLower.cpp
[RISCV] Add lowering of global TLS addresses
2019-06-19 08:40:59 +00:00
RISCVMergeBaseOffset.cpp
[RISCV] Convert registers from unsigned to Register
2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterBankInfo.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterBanks.td
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVRegisterInfo.h
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVRegisterInfo.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVSubtarget.cpp
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVSubtarget.h
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVSystemOperands.td
[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references
2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVTargetMachine.h
[RISCV] Add RISCV-specific TargetTransformInfo
2019-06-21 13:36:09 +00:00
RISCVTargetObjectFile.cpp
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
RISCVTargetObjectFile.h
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp
[RISCV] Fix RISCVTTIImpl::getIntImmCost for immediates where getMinSignedBits() > 64
2019-07-09 10:56:18 +00:00
RISCVTargetTransformInfo.h
[RISCV] Add RISCV-specific TargetTransformInfo
2019-06-21 13:36:09 +00:00