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llvm-mirror/test/MC/Hexagon/not-over.s
Krzysztof Parzyszek df7d452980 [Hexagon] Update MCTargetDesc
Changes include:
- Updates to the instruction descriptor flags.
- Improvements to the packet shuffler and checker.
- Updates to the handling of certain relocations.
- Better handling of duplex instructions.

llvm-svn: 294226
2017-02-06 19:35:46 +00:00

56 lines
1.2 KiB
ArmAsm

# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
#
# Check that proper packets are not wrongly flagged as invalid.
1-3-4-f:
{
r3 = memub(r2++#1)
if (cmp.eq(r3.new,#0)) jump:nt .
jumpr lr
r4 = #4
}
# CHECK-NOT: rror: invalid instruction packet
1-3-f-f:
{
r3 = memub(r2++#1)
if (cmp.eq(r3.new,#0)) jump:nt .
r5 = #5
r4 = #4
}
# CHECK-NOT: rror: invalid instruction packet
# Special case of a fat packet that will slim when a compound is formed.
3-3-8-c:
{ LOOP0(3-3-8-c, R7)
P0 = CMP.GT(R7, #0)
IF (!P0.NEW) JUMP:NT .
R21:20 = MEMD(R0+#16)
R23:22 = MEMD(R0+#24)
}
# CHECK-NOT: rror: invalid instruction packet
1-f-f-f:
{
r3 = #3
if (cmp.eq(r3.new,#0)) jump:nt .
r5 = #5
r4 = #4
}
# CHECK-NOT: rror: invalid instruction packet
4:
jumpr lr
# CHECK-NOT: rror: invalid instruction packet
f-f-f-f:
{
r3 = #3
r2 = #2
r5 = #5
r4 = #4
}
# CHECK-NOT: rror: invalid instruction packet