David Green 301346d47a [LSR] Don't require register reuse under postinc ... LSR has some logic that tries to aggressively reuse registers in formula. This can lead to sub-optimal decision in complex loops where the backend it trying to use shouldFavorPostInc. This disables the re-use in those situations. Differential Revision: https://reviews.llvm.org/D79301		2020-05-05 16:04:50 +01:00
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AArch64	[AArch64][SVE] Guard bitcast patterns under IsLE predicate	2020-05-05 13:18:35 +01:00
AMDGPU	[AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizer	2020-05-05 15:49:09 +01:00
ARC
ARM	[ARM] Fix tail call validity checking for varargs calls.	2020-05-04 12:34:14 -07:00
AVR
BPF
Generic
Hexagon	[RegisterCoalescer] Extend a subrange if needed when filling range gap	2020-05-04 16:49:59 -05:00
Inputs
Lanai
Mips	[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values	2020-05-04 14:44:39 +01:00
MIR
MSP430
NVPTX
PowerPC	[PowerPC][AIX][NFC] Remove spills and reloads from arg passing test.	2020-05-04 14:26:33 -04:00
RISCV
SPARC
SystemZ
Thumb
Thumb2	[LSR] Don't require register reuse under postinc	2020-05-05 16:04:50 +01:00
VE
WebAssembly	[WebAssembly] Fix block marker placing after fixUnwindMismatches	2020-05-05 02:06:47 -07:00
WinCFGuard
WinEH
X86	[X86][AVX] combineVectorSignBitsTruncation - avoid complex vXi64->vXi32 PACKSS truncations (PR45794)	2020-05-05 11:57:25 +01:00
XCore