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Unoptimized IR can have linear sequences of stores to an array, where the initial GEP for the first store is formed from the pointer to the array, and the GEP for each store after the first is formed from the previous GEP with some offset in an inductive fashion. The (large) resulting DAG when analyzed by DAGCombine undergoes an excessive number of combines as each store node is examined every time its' offset node is combined with any child of the offset. One of the transformations is findBetterNeighborChains which assists MergeConsecutiveStores. The former relies on repeated chain walking to do its' work, however MergeConsecutiveStores is disabled at O0 which makes the transformation redundant. Any optimization level other than O0 would invoke InstCombine which would resolve the chain of GEPs into flat base + offset GEP for each store which does not exhibit the repeated examination of each store to the array. Disabling this optimization fixes an excessive compile time issue (30~ minutes for the test case provided) at O0. Reviewers: niravd, craig.topper, t.p.northover Differential Revision: https://reviews.llvm.org/D40193 llvm-svn: 319142
83 lines
3.7 KiB
LLVM
83 lines
3.7 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s
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; rdar://12713765
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; When realign-stack is set to false, make sure we are not creating stack
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; objects that are assumed to be 64-byte aligned.
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@T3_retval = common global <16 x float> zeroinitializer, align 16
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define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
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entry:
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; CHECK-LABEL: test1:
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; CHECK: ldr r[[R1:[0-9]+]], [pc, r[[R1]]]
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; CHECK: mov r[[R2:[0-9]+]], r[[R1]]
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; CHECK: vld1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R2]]:128]!
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R2]]:128]
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; CHECK: add r[[R3:[0-9]+]], r[[R1]], #32
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R3]]:128]
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; CHECK: add r[[R3:[0-9]+]], r[[R1]], #48
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R3]]:128]
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; CHECK: mov r[[R2:[0-9]+]], sp
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; CHECK: add r[[R3:[0-9]+]], r[[R2]], #48
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R3]]:128]
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; CHECK: add r[[R4:[0-9]+]], r[[R2]], #32
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R4]]:128]
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; CHECK: mov r[[R5:[0-9]+]], r[[R2]]
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; CHECK: vst1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R5]]:128]!
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R5]]:128]
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R5]]:128]
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R2]]:128]
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R4]]:128]
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R3]]:128]
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; CHECK: add r[[R1:[0-9]+]], r0, #48
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R1]]:128]
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; CHECK: add r[[R1:[0-9]+]], r0, #32
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R1]]:128]
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; CHECK: vst1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0:128]!
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0:128]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>, <16 x float>* @T3_retval, align 16
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store <16 x float> %0, <16 x float>* %retval
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%1 = load <16 x float>, <16 x float>* %retval
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store <16 x float> %1, <16 x float>* %agg.result, align 16
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ret void
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}
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define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
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entry:
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; CHECK-LABEL: test2:
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; CHECK: ldr r[[R1:[0-9]+]], [pc, r[[R1]]]
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; CHECK: add r[[R2:[0-9]+]], r[[R1]], #48
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R2]]:128]
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; CHECK: add r[[R2:[0-9]+]], r[[R1]], #32
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R2]]:128]
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; CHECK: vld1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R1]]:128]!
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R1]]:128]
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; CHECK: mov r[[R1:[0-9]+]], sp
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; CHECK: orr r[[R2:[0-9]+]], r[[R1]], #16
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R2]]:128]
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; CHECK: mov r[[R3:[0-9]+]], #32
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; CHECK: mov r[[R9:[0-9]+]], r[[R1]]
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; CHECK: vst1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R9]]:128], r[[R3]]
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; CHECK: mov r[[R3:[0-9]+]], r[[R9]]
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; CHECK: vst1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R3]]:128]!
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R3]]:128]
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R9]]:128]
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R3]]:128]
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R2]]:128]
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; CHECK: vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R1]]:128]
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; CHECK: add r[[R1:[0-9]+]], r0, #48
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R1]]:128]
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; CHECK: add r[[R1:[0-9]+]], r0, #32
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r[[R1]]:128]
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; CHECK: vst1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0:128]!
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; CHECK: vst1.64 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0:128]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>, <16 x float>* @T3_retval, align 16
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store <16 x float> %0, <16 x float>* %retval
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%1 = load <16 x float>, <16 x float>* %retval
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store <16 x float> %1, <16 x float>* %agg.result, align 16
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ret void
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}
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