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029d974b53
Summary:
Two utils methods have essentially the same functionality. This is an attempt to merge them into one.
1. lib/Transforms/Utils/Local.cpp : MergeBasicBlockIntoOnlyPred
2. lib/Transforms/Utils/BasicBlockUtils.cpp : MergeBlockIntoPredecessor
Prior to the patch:
1. MergeBasicBlockIntoOnlyPred
Updates either DomTree or DeferredDominance
Moves all instructions from Pred to BB, deletes Pred
Asserts BB has single predecessor
If address was taken, replace the block address with constant 1 (?)
2. MergeBlockIntoPredecessor
Updates DomTree, LoopInfo and MemoryDependenceResults
Moves all instruction from BB to Pred, deletes BB
Returns if doesn't have a single predecessor
Returns if BB's address was taken
After the patch:
Method 2. MergeBlockIntoPredecessor is attempting to become the new default:
Updates DomTree or DeferredDominance, and LoopInfo and MemoryDependenceResults
Moves all instruction from BB to Pred, deletes BB
Returns if doesn't have a single predecessor
Returns if BB's address was taken
Uses of MergeBasicBlockIntoOnlyPred that need to be replaced:
1. lib/Transforms/Scalar/LoopSimplifyCFG.cpp
Updated in this patch. No challenges.
2. lib/CodeGen/CodeGenPrepare.cpp
Updated in this patch.
i. eliminateFallThrough is straightforward, but I added using a temporary array to avoid the iterator invalidation.
ii. eliminateMostlyEmptyBlock(s) methods also now use a temporary array for blocks
Some interesting aspects:
- Since Pred is not deleted (BB is), the entry block does not need updating.
- The entry block was being updated with the deleted block in eliminateMostlyEmptyBlock. Added assert to make obvious that BB=SinglePred.
- isMergingEmptyBlockProfitable assumes BB is the one to be deleted.
- eliminateMostlyEmptyBlock(BB) does not delete BB on one path, it deletes its unique predecessor instead.
- adding some test owner as subscribers for the interesting tests modified:
test/CodeGen/X86/avx-cmp.ll
test/CodeGen/AMDGPU/nested-loop-conditions.ll
test/CodeGen/AMDGPU/si-annotate-cf.ll
test/CodeGen/X86/hoist-spill.ll
test/CodeGen/X86/2006-11-17-IllegalMove.ll
3. lib/Transforms/Scalar/JumpThreading.cpp
Not covered in this patch. It is the only use case using the DeferredDominance.
I would defer to Brian Rzycki to make this replacement.
Reviewers: chandlerc, spatel, davide, brzycki, bkramer, javed.absar
Subscribers: qcolombet, sanjoy, nemanjai, nhaehnle, jlebar, tpr, kbarton, RKSimon, wmi, arsenm, llvm-commits
Differential Revision: https://reviews.llvm.org/D48202
llvm-svn: 335183
79 lines
3.2 KiB
LLVM
79 lines
3.2 KiB
LLVM
; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM
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; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB
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; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2
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; RUN: llc < %s -relocation-model=static -mtriple=thumbv8-apple-darwin | FileCheck %s -check-prefix=THUMB2
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@nextaddr = global i8* null ; <i8**> [#uses=2]
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@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
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define internal i32 @foo(i32 %i) nounwind {
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; ARM-LABEL: foo:
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; THUMB-LABEL: foo:
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; THUMB2-LABEL: foo:
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entry:
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; _nextaddr gets CSEed for use later on.
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; THUMB: ldr r[[NEXTADDR_REG:[0-9]+]], [[NEXTADDR_CPI:LCPI0_[0-9]+]]
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; THUMB: [[NEXTADDR_PCBASE:LPC0_[0-9]]]:
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; THUMB: add r[[NEXTADDR_REG]], pc
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%0 = load i8*, i8** @nextaddr, align 4 ; <i8*> [#uses=2]
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%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
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; indirect branch gets duplicated here
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; ARM: bx
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; THUMB: mov pc,
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; THUMB2: mov pc,
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br i1 %1, label %bb3, label %bb2
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bb2: ; preds = %entry, %bb3
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%gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
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; ARM: bx
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; THUMB: mov pc,
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indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
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bb3: ; preds = %entry
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%2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
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%gotovar.4.0.pre = load i8*, i8** %2, align 4 ; <i8*> [#uses=1]
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br label %bb2
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L5: ; preds = %bb2
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br label %L4
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L4: ; preds = %L5, %bb2
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%res.0 = phi i32 [ 385, %L5 ], [ 35, %bb2 ] ; <i32> [#uses=1]
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br label %L3
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L3: ; preds = %L4, %bb2
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%res.1 = phi i32 [ %res.0, %L4 ], [ 5, %bb2 ] ; <i32> [#uses=1]
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br label %L2
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L2: ; preds = %L3, %bb2
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; THUMB-LABEL: %.split4
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; THUMB: muls
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%res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1]
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%phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1]
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br label %L1
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L1: ; preds = %L2, %bb2
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%res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
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; ARM-LABEL: %L1
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; ARM: ldr [[R_NEXTADDR:r[0-9]+]], LCPI
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; ARM: ldr [[R1:r[0-9]+]], LCPI
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; ARM: add [[R_NEXTADDR_b:r[0-9]+]], pc, [[R_NEXTADDR]]
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; ARM: add [[R1b:r[0-9]+]], pc, [[R1]]
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; ARM: str [[R1b]], {{\[}}[[R_NEXTADDR_b]]]
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; THUMB-LABEL: %L1
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; THUMB: ldr [[R2:r[0-9]+]], LCPI
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; THUMB: add [[R2]], pc
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; THUMB: str [[R2]], [r[[NEXTADDR_REG]]]
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; THUMB2-LABEL: %L1
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; THUMB2: ldr [[R2:r[0-9]+]], LCPI
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; THUMB2-NEXT: str{{(.w)?}} [[R2]]
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store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
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ret i32 %res.3
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}
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; ARM: .long Ltmp0-(LPC{{.*}}+8)
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; THUMB: .long Ltmp0-(LPC{{.*}}+4)
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; THUMB: .long _nextaddr-([[NEXTADDR_PCBASE]]+4)
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; THUMB2: .long Ltmp0
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