mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 02:52:53 +02:00
03e7233966
For targets that don't have ISD::MULHS or ISD::SMUL_LOHI for the type and the double width type is illegal, then the two operands are sign extended to twice their size then multiplied to check for overflow. The extended upper halves were mismatched causing an incorrect result. This fixes the mismatch. A test was added for ARM V6-M where the bug was detected. Patch by James Duley. Differential Revision: https://reviews.llvm.org/D31807 llvm-svn: 301404
17 lines
477 B
LLVM
17 lines
477 B
LLVM
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
|
|
|
|
define i1 @signed_multiplication_did_overflow(i32, i32) {
|
|
; CHECK-LABEL: signed_multiplication_did_overflow:
|
|
entry-block:
|
|
%2 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %1)
|
|
%3 = extractvalue { i32, i1 } %2, 1
|
|
ret i1 %3
|
|
|
|
; CHECK: mov r2, r1
|
|
; CHECK: asrs r1, r0, #31
|
|
; CHECK: asrs r3, r2, #31
|
|
; CHECK: bl __aeabi_lmul
|
|
}
|
|
|
|
declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
|