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https://github.com/RPCS3/llvm-mirror.git
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7ed143a4a1
Printing floating point number in decimal is inconvenient for humans. Verbose asm output will print out floating point values in comments, it helps. But in lots of cases, users still need additional work to covert the decimal back to hex or binary to check the bit patterns, especially when there are small precision difference. Hexadecimal form is one of the supported form in LLVM IR, and easier for debugging. This patch try to print all FP constant in hex form instead. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D73566
167 lines
5.7 KiB
LLVM
167 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half, <1 x half>)
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float, <1 x float>)
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declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double, <1 x double>)
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declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128, <1 x fp128>)
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float, <3 x float>)
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declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>)
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float, <16 x float>)
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define half @test_v1f16(<1 x half> %a) nounwind {
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; CHECK-LABEL: test_v1f16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: bl __aeabi_f2h
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: vldr s0, .LCPI0_0
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; CHECK-NEXT: vmov s2, r0
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; CHECK-NEXT: vadd.f32 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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%b = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a)
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ret half %b
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}
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define float @test_v1f32(<1 x float> %a) nounwind {
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; CHECK-LABEL: test_v1f32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr s0, .LCPI1_0
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; CHECK-NEXT: vmov s2, r0
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; CHECK-NEXT: vadd.f32 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: mov pc, lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI1_0:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a)
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ret float %b
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}
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define double @test_v1f64(<1 x double> %a) nounwind {
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; CHECK-LABEL: test_v1f64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 d16, #0x0
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; CHECK-NEXT: vmov d17, r0, r1
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; CHECK-NEXT: vadd.f64 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%b = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double 0.0, <1 x double> %a)
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ret double %b
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}
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define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v1f128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: str r12, [sp]
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; CHECK-NEXT: str r12, [sp, #4]
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; CHECK-NEXT: str r12, [sp, #8]
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; CHECK-NEXT: str r12, [sp, #12]
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; CHECK-NEXT: bl __addtf3
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v3f32(<3 x float> %a) nounwind {
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; CHECK-LABEL: test_v3f32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov d3, r2, r3
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; CHECK-NEXT: vldr s0, .LCPI4_0
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; CHECK-NEXT: vmov d2, r0, r1
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; CHECK-NEXT: vadd.f32 s0, s4, s0
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; CHECK-NEXT: vadd.f32 s0, s0, s5
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; CHECK-NEXT: vadd.f32 s0, s0, s6
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: mov pc, lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI4_0:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a)
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ret float %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r11, lr}
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; CHECK-NEXT: push {r4, r5, r11, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: str r12, [sp]
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; CHECK-NEXT: str r12, [sp, #4]
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; CHECK-NEXT: str r12, [sp, #8]
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; CHECK-NEXT: str r12, [sp, #12]
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; CHECK-NEXT: bl __addtf3
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; CHECK-NEXT: ldr r12, [sp, #36]
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; CHECK-NEXT: ldr lr, [sp, #32]
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; CHECK-NEXT: ldr r4, [sp, #40]
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; CHECK-NEXT: ldr r5, [sp, #44]
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; CHECK-NEXT: str lr, [sp]
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; CHECK-NEXT: str r12, [sp, #4]
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; CHECK-NEXT: str r4, [sp, #8]
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; CHECK-NEXT: str r5, [sp, #12]
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; CHECK-NEXT: bl __addtf3
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: pop {r4, r5, r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v16f32(<16 x float> %a) nounwind {
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; CHECK-LABEL: test_v16f32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov d3, r2, r3
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; CHECK-NEXT: vldr s0, .LCPI6_0
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; CHECK-NEXT: vmov d2, r0, r1
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vadd.f32 s0, s4, s0
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; CHECK-NEXT: vadd.f32 s0, s0, s5
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; CHECK-NEXT: vadd.f32 s0, s0, s6
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; CHECK-NEXT: vadd.f32 s0, s0, s7
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; CHECK-NEXT: vld1.64 {d2, d3}, [r0]
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; CHECK-NEXT: add r0, sp, #16
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; CHECK-NEXT: vadd.f32 s0, s0, s4
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; CHECK-NEXT: vadd.f32 s0, s0, s5
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; CHECK-NEXT: vadd.f32 s0, s0, s6
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; CHECK-NEXT: vadd.f32 s0, s0, s7
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; CHECK-NEXT: vld1.64 {d2, d3}, [r0]
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; CHECK-NEXT: add r0, sp, #32
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; CHECK-NEXT: vadd.f32 s0, s0, s4
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; CHECK-NEXT: vadd.f32 s0, s0, s5
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; CHECK-NEXT: vadd.f32 s0, s0, s6
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; CHECK-NEXT: vadd.f32 s0, s0, s7
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; CHECK-NEXT: vld1.64 {d2, d3}, [r0]
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; CHECK-NEXT: vadd.f32 s0, s0, s4
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; CHECK-NEXT: vadd.f32 s0, s0, s5
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; CHECK-NEXT: vadd.f32 s0, s0, s6
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; CHECK-NEXT: vadd.f32 s0, s0, s7
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: mov pc, lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI6_0:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a)
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ret float %b
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}
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