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02feb4f599
An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in single-float mode. This would trigger an "Unexpected illegal type!" assert. Patch by Dan Ravensloft. Differential revision: https://reviews.llvm.org/D51810 llvm-svn: 341952
53 lines
1.8 KiB
LLVM
53 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=mips64el-mti-linux-gnu -mattr=+single-float < %s | FileCheck %s
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; This test casts a 32-bit float to a 64-bit int. This would cause a crash due
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; to LLVM incorrectly lowering the float on single-float platforms.
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define void @foo(float* %in, i64* %out) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: daddiu $sp, $sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sd $5, 0($sp)
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; CHECK-NEXT: sd $4, 8($sp)
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; CHECK-NEXT: lwc1 $f0, 0($4)
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; CHECK-NEXT: mfc1 $1, $f0
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; CHECK-NEXT: lui $2, 32640
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; CHECK-NEXT: and $2, $1, $2
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; CHECK-NEXT: srl $2, $2, 23
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; CHECK-NEXT: lui $3, 127
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; CHECK-NEXT: ori $3, $3, 65535
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; CHECK-NEXT: addiu $4, $zero, 150
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; CHECK-NEXT: subu $4, $4, $2
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; CHECK-NEXT: and $3, $1, $3
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; CHECK-NEXT: lui $6, 128
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; CHECK-NEXT: or $3, $3, $6
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; CHECK-NEXT: dsll $3, $3, 32
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; CHECK-NEXT: dsrl $3, $3, 32
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; CHECK-NEXT: dsrlv $4, $3, $4
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; CHECK-NEXT: addiu $6, $2, -150
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; CHECK-NEXT: dsllv $3, $3, $6
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; CHECK-NEXT: addiu $2, $2, -127
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; CHECK-NEXT: slti $6, $2, 24
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; CHECK-NEXT: movz $4, $3, $6
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; CHECK-NEXT: sra $1, $1, 31
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; CHECK-NEXT: xor $3, $4, $1
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; CHECK-NEXT: dsubu $1, $3, $1
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; CHECK-NEXT: slti $2, $2, 0
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; CHECK-NEXT: movn $1, $zero, $2
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; CHECK-NEXT: sd $1, 0($5)
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $sp, $sp, 16
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entry:
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%in.addr = alloca float*, align 8
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%out.addr = alloca i64*, align 8
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store float* %in, float** %in.addr, align 8
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store i64* %out, i64** %out.addr, align 8
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%0 = load float*, float** %in.addr, align 8
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%1 = load float, float* %0, align 4
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%conv = fptosi float %1 to i64
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%2 = load i64*, i64** %out.addr, align 8
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store i64 %conv, i64* %2, align 8
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ret void
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}
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