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45 lines
2.0 KiB
ArmAsm
45 lines
2.0 KiB
ArmAsm
// RUN: llvm-mc -triple=aarch64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s
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// RUN: not llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO %s
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// Check that the assembler can handle the documented syntax for AArch64
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//------------------------------------------------------------------------------
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// Instructions for crypto
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//------------------------------------------------------------------------------
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aese v0.16b, v1.16b
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aesd v0.16b, v1.16b
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aesmc v0.16b, v1.16b
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aesimc v0.16b, v1.16b
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// CHECK-NO-CRYPTO: error: instruction requires a CPU feature not currently enabled
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// CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e]
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// CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e]
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// CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e]
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// CHECK: aesimc v0.16b, v1.16b // encoding: [0x20,0x78,0x28,0x4e]
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sha1h s0, s1
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sha1su1 v0.4s, v1.4s
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sha256su0 v0.4s, v1.4s
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// CHECK: sha1h s0, s1 // encoding: [0x20,0x08,0x28,0x5e]
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// CHECK: sha1su1 v0.4s, v1.4s // encoding: [0x20,0x18,0x28,0x5e]
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// CHECK: sha256su0 v0.4s, v1.4s // encoding: [0x20,0x28,0x28,0x5e]
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sha1c q0, s1, v2.4s
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sha1p q0, s1, v2.4s
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sha1m q0, s1, v2.4s
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sha1su0 v0.4s, v1.4s, v2.4s
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sha256h q0, q1, v2.4s
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sha256h2 q0, q1, v2.4s
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sha256su1 v0.4s, v1.4s, v2.4s
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// CHECK: sha1c q0, s1, v2.4s // encoding: [0x20,0x00,0x02,0x5e]
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// CHECK: sha1p q0, s1, v2.4s // encoding: [0x20,0x10,0x02,0x5e]
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// CHECK: sha1m q0, s1, v2.4s // encoding: [0x20,0x20,0x02,0x5e]
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// CHECK: sha1su0 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x30,0x02,0x5e]
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// CHECK: sha256h q0, q1, v2.4s // encoding: [0x20,0x40,0x02,0x5e]
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// CHECK: sha256h2 q0, q1, v2.4s // encoding: [0x20,0x50,0x02,0x5e]
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// CHECK: sha256su1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x60,0x02,0x5e]
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