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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 11:02:59 +02:00
llvm-mirror/test/CodeGen
Lei Huang e9a9e6af23 [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
Summary:
This patch simply adds support for the new CPU in anticipation of
Power10. There isn't really any functionality added so there are no
associated test cases at this time.

Reviewers: stefanp, nemanjai, amyk, hfinkel, power-llvm-team, #powerpc

Reviewed By: stefanp, nemanjai, amyk, #powerpc

Subscribers: NeHuang, steven.zhang, hiraditya, llvm-commits, wuzish, shchenz, cfe-commits, kbarton, echristo

Tags: #clang, #powerpc, #llvm

Differential Revision: https://reviews.llvm.org/D80020
2020-05-26 13:48:22 -05:00
..
AArch64 GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic 2020-05-26 11:48:13 -04:00
AMDGPU AMDGPU/GlobalISel: Fix assert on 16-bit G_EXTRACT results 2020-05-26 12:14:08 -04:00
ARC
ARM [TargetPassConfig] Don't add alias analysis at optnone 2020-05-23 10:35:03 +02:00
AVR
BPF [BPF] Return fail if disassembled insn registers out of range 2020-05-18 18:53:23 -07:00
Generic [FPEnv] Intrinsic llvm.roundeven 2020-05-26 19:24:58 +07:00
Hexagon
Inputs
Lanai
Mips Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC" 2020-05-22 05:36:15 -06:00
MIR
MSP430
NVPTX
PowerPC [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm 2020-05-26 13:48:22 -05:00
RISCV
SPARC
SystemZ [SystemZ] Eliminate the need to create a zero vector by reusing the VPERM mask. 2020-05-19 09:37:19 +02:00
Thumb
Thumb2 [ARM] MVE VMINV/VMAXV test additions. NFC 2020-05-26 14:00:14 +01:00
VE [VE][NFC] Correct sjlj_expection test 2020-05-25 09:49:37 +02:00
WebAssembly [WebAssembly] Fix bug in custom shuffle combine 2020-05-19 12:54:15 -07:00
WinCFGuard
WinEH
X86 [DAGCombiner] try to move splat after binop with splat constant 2020-05-26 08:12:46 -04:00
XCore