Artyom Skrobov 312bcfdb97 [ARM] Allow SP in rGPR, starting from ARMv8 ... Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516		2015-10-28 13:58:36 +00:00
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AArch64	[AArch64] Check the size of the vector before accessing its elements.	2015-10-13 18:55:34 +00:00
AMDGPU	AMDGPU: Fix parsing of 32-bit literals with sign bit set	2015-10-23 18:07:58 +00:00
ARM	[ARM] Allow SP in rGPR, starting from ARMv8	2015-10-28 13:58:36 +00:00
AsmParser	[MC] Don't crash when .word is given bogus values	2015-10-26 02:45:50 +00:00
COFF	Fix pr24486.	2015-10-05 12:07:05 +00:00
Disassembler	[ARM] Allow SP in rGPR, starting from ARMv8	2015-10-28 13:58:36 +00:00
ELF	Fix pr24486.	2015-10-05 12:07:05 +00:00
Hexagon	[Hexagon] Split double registers	2015-10-16 20:38:54 +00:00
MachO	[MachO] Stop generating *coal* sections.	2015-10-15 05:28:38 +00:00
Markup
Mips	[mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions	2015-10-28 11:04:29 +00:00
PowerPC	[PowerPC] Replace cntlz[.] with cntlzw[.]	2015-10-28 03:26:45 +00:00
Sparc	Update test to take into account for r251271.	2015-10-26 03:34:29 +00:00
SystemZ	[SystemZ] testcase MC/SystemZ/insn-good-z13.s extended.	2015-10-12 10:13:57 +00:00
X86	[X86][AVX512] [X86][AVX512] add convert float to half	2015-10-27 15:37:17 +00:00