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6ffdf68855
in exposing the scalar value to the broadcast DAG fragment so that we can catch even reloads and fold them into the broadcast. This is somewhat magical I'm afraid but seems to work. It is also what the old lowering did, and I've switched an old test to run both lowerings demonstrating that we get the same result. Unlike the old code, I'm not lowering f32 or f64 scalars through this path when we only have AVX1. The target patterns include pretty heinous code to re-cast those as shuffles when the scalar happens to not be spilled because AVX1 provides no broadcast mechanism from registers what-so-ever. This is terribly brittle. I'd much rather go through our generic lowering code to get this. If needed, we can add a peephole to get even more opportunities to broadcast-from-spill-slots that are exposed post-RA, but my suspicion is this just doesn't matter that much. llvm-svn: 218734
25 lines
773 B
LLVM
25 lines
773 B
LLVM
; RUN: llc < %s -march=x86 -mcpu=corei7 -mattr=+avx2 | FileCheck %s
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; RUN: llc < %s -march=x86 -mcpu=corei7 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s
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declare x86_fastcallcc i64 @barrier()
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;CHECK-LABEL: bcast_fold:
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;CHECK: vmov{{[au]}}ps %xmm{{[0-9]+}}, [[SPILLED:[^\)]+\)]]
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;CHECK: barrier
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;CHECK: vbroadcastss [[SPILLED]], %ymm0
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;CHECK: ret
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define <8 x float> @bcast_fold( float* %A) {
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BB:
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%A0 = load float* %A
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%tt3 = call x86_fastcallcc i64 @barrier()
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br i1 undef, label %work, label %exit
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work:
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%A1 = insertelement <8 x float> undef, float %A0, i32 0
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%A2 = shufflevector <8 x float> %A1, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x float> %A2
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exit:
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ret <8 x float> undef
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}
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