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0620939033
Summary: Move reserveRegisterTuples into AMDGPURegisterInfo and use it in R600RegisterInfo::getReservedRegs and R600InstrInfo::reserveIndirectRegisters to ensure that all super registers of reserved registers are also marked as reserved. Before this change, under certain circumstances, the registers %t1_x and %t1_xyzw would be marked as reserved, but %t1_xy and %t1_xyz would not be, leading to the register allocator sometimes assigning a register to %t1_xy, which is invalid since %t1_x is reserved. Reviewers: arsenm, tstellar, MatzeB, qcolombet Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D42448 llvm-svn: 323356
111 lines
3.5 KiB
C++
111 lines
3.5 KiB
C++
//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "R600RegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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using namespace llvm;
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R600RegisterInfo::R600RegisterInfo() : AMDGPURegisterInfo() {
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RCW.RegWeight = 0;
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RCW.WeightLimit = 0;
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}
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BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
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const R600InstrInfo *TII = ST.getInstrInfo();
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reserveRegisterTuples(Reserved, AMDGPU::ZERO);
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reserveRegisterTuples(Reserved, AMDGPU::HALF);
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reserveRegisterTuples(Reserved, AMDGPU::ONE);
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reserveRegisterTuples(Reserved, AMDGPU::ONE_INT);
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reserveRegisterTuples(Reserved, AMDGPU::NEG_HALF);
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reserveRegisterTuples(Reserved, AMDGPU::NEG_ONE);
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reserveRegisterTuples(Reserved, AMDGPU::PV_X);
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reserveRegisterTuples(Reserved, AMDGPU::ALU_LITERAL_X);
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reserveRegisterTuples(Reserved, AMDGPU::ALU_CONST);
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reserveRegisterTuples(Reserved, AMDGPU::PREDICATE_BIT);
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reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_OFF);
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reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ZERO);
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reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ONE);
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reserveRegisterTuples(Reserved, AMDGPU::INDIRECT_BASE_ADDR);
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for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
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E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
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reserveRegisterTuples(Reserved, *I);
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}
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TII->reserveIndirectRegisters(Reserved, MF, *this);
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return Reserved;
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}
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// Dummy to not crash RegisterClassInfo.
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static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister;
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const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
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const MachineFunction *) const {
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return &CalleeSavedReg;
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}
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unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return AMDGPU::NoRegister;
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}
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unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
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return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
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}
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unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
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return GET_REG_INDEX(getEncodingValue(Reg));
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}
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const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
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}
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}
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const RegClassWeight &R600RegisterInfo::getRegClassWeight(
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const TargetRegisterClass *RC) const {
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return RCW;
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}
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bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
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assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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switch (Reg) {
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case AMDGPU::OQAP:
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case AMDGPU::OQBP:
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case AMDGPU::AR_X:
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return false;
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default:
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return true;
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}
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}
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void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const {
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llvm_unreachable("Subroutines not supported yet");
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}
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