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c21c095194
This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.
This is an example of a function's body that uses the old syntax:
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- 'RETQ %eax'
...
The same body is now written like this:
body: |
bb.0.entry:
%eax = MOV32r0 implicit-def %eflags
RETQ %eax
...
This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:
BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
t2IT 1, 24, implicit-def %itstate
%s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
}
This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.
llvm-svn: 244982
65 lines
2.2 KiB
YAML
65 lines
2.2 KiB
YAML
# RUN: not llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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%struct.foo = type { float, [5 x i32] }
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@float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4
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define void @float(float addrspace(1)* %out, i32 %index) #0 {
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entry:
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%0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
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%1 = load float, float addrspace(2)* %0
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store float %1, float addrspace(1)* %out
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ret void
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}
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declare { i1, i64 } @llvm.SI.if(i1)
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declare { i1, i64 } @llvm.SI.else(i64)
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declare i64 @llvm.SI.break(i64)
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declare i64 @llvm.SI.if.break(i1, i64)
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declare i64 @llvm.SI.else.break(i64, i64)
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declare i1 @llvm.SI.loop(i64)
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declare void @llvm.SI.end.cf(i64)
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attributes #0 = { "target-cpu"="SI" }
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...
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---
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name: float
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tracksSubRegLiveness: true
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liveins:
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- { reg: '%sgpr0_sgpr1' }
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frameInfo:
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maxAlignment: 8
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body: |
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bb.0.entry:
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liveins: %sgpr0_sgpr1
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%sgpr2_sgpr3 = S_GETPC_B64
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; CHECK: [[@LINE+1]]:45: expected the name of the target index
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%sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc
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%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
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%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
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%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
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%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
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%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
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%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
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%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
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%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
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%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
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%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
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%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
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%sgpr7 = S_MOV_B32 61440
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%sgpr6 = S_MOV_B32 -1
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%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
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BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
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S_ENDPGM
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...
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