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295 lines
8.8 KiB
C++
295 lines
8.8 KiB
C++
//===- MBlazeInstrInfo.h - MBlaze Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MBlaze implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MBLAZEINSTRUCTIONINFO_H
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#define MBLAZEINSTRUCTIONINFO_H
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#include "MBlaze.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "MBlazeRegisterInfo.h"
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namespace llvm {
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namespace MBlaze {
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// MBlaze Branch Codes
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enum FPBranchCode {
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BRANCH_F,
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BRANCH_T,
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BRANCH_FL,
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BRANCH_TL,
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BRANCH_INVALID
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};
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// MBlaze Condition Codes
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enum CondCode {
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// To be used with float branch True
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FCOND_F,
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FCOND_UN,
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FCOND_EQ,
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FCOND_UEQ,
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FCOND_OLT,
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FCOND_ULT,
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FCOND_OLE,
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FCOND_ULE,
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FCOND_SF,
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FCOND_NGLE,
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FCOND_SEQ,
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FCOND_NGL,
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FCOND_LT,
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FCOND_NGE,
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FCOND_LE,
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FCOND_NGT,
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// To be used with float branch False
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// This conditions have the same mnemonic as the
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// above ones, but are used with a branch False;
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FCOND_T,
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FCOND_OR,
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FCOND_NEQ,
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FCOND_OGL,
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FCOND_UGE,
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FCOND_OGE,
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FCOND_UGT,
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FCOND_OGT,
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FCOND_ST,
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FCOND_GLE,
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FCOND_SNE,
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FCOND_GL,
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FCOND_NLT,
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FCOND_GE,
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FCOND_NLE,
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FCOND_GT,
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// Only integer conditions
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COND_EQ,
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COND_GT,
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COND_GE,
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COND_LT,
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COND_LE,
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COND_NE,
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COND_INVALID
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};
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// Turn condition code into conditional branch opcode.
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inline static unsigned GetCondBranchFromCond(CondCode CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case COND_EQ: return MBlaze::BEQID;
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case COND_NE: return MBlaze::BNEID;
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case COND_GT: return MBlaze::BGTID;
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case COND_GE: return MBlaze::BGEID;
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case COND_LT: return MBlaze::BLTID;
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case COND_LE: return MBlaze::BLEID;
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}
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}
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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// CondCode GetOppositeBranchCondition(MBlaze::CondCode CC);
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/// MBlazeCCToString - Map each FP condition code to its string
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inline static const char *MBlazeFCCToString(MBlaze::CondCode CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case FCOND_F:
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case FCOND_T: return "f";
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case FCOND_UN:
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case FCOND_OR: return "un";
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case FCOND_EQ:
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case FCOND_NEQ: return "eq";
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case FCOND_UEQ:
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case FCOND_OGL: return "ueq";
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case FCOND_OLT:
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case FCOND_UGE: return "olt";
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case FCOND_ULT:
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case FCOND_OGE: return "ult";
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case FCOND_OLE:
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case FCOND_UGT: return "ole";
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case FCOND_ULE:
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case FCOND_OGT: return "ule";
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case FCOND_SF:
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case FCOND_ST: return "sf";
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case FCOND_NGLE:
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case FCOND_GLE: return "ngle";
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case FCOND_SEQ:
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case FCOND_SNE: return "seq";
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case FCOND_NGL:
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case FCOND_GL: return "ngl";
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case FCOND_LT:
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case FCOND_NLT: return "lt";
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case FCOND_NGE:
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case FCOND_GE: return "ge";
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case FCOND_LE:
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case FCOND_NLE: return "nle";
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case FCOND_NGT:
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case FCOND_GT: return "gt";
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}
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}
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inline static bool isUncondBranchOpcode(int Opc) {
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switch (Opc) {
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default: return false;
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case MBlaze::BRI:
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case MBlaze::BRAI:
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case MBlaze::BRID:
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case MBlaze::BRAID:
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return true;
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}
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}
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inline static bool isCondBranchOpcode(int Opc) {
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switch (Opc) {
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default: return false;
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case MBlaze::BEQI: case MBlaze::BEQID:
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case MBlaze::BNEI: case MBlaze::BNEID:
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case MBlaze::BGTI: case MBlaze::BGTID:
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case MBlaze::BGEI: case MBlaze::BGEID:
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case MBlaze::BLTI: case MBlaze::BLTID:
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case MBlaze::BLEI: case MBlaze::BLEID:
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return true;
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}
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}
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}
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/// MBlazeII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace MBlazeII {
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enum {
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// PseudoFrm - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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FPseudo = 0,
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FRRR,
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FRRI,
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FCRR,
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FCRI,
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FRCR,
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FRCI,
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FCCR,
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FCCI,
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FRRCI,
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FRRC,
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FRCX,
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FRCS,
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FCRCS,
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FCRCX,
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FCX,
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FCR,
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FRIR,
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FRRRR,
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FRI,
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FC,
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FormMask = 63
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//===------------------------------------------------------------------===//
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// MBlaze Specific MachineOperand flags.
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// MO_NO_FLAG,
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/// MO_GOT - Represents the offset into the global offset table at which
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/// the address the relocation entry symbol resides during execution.
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// MO_GOT,
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/// MO_GOT_CALL - Represents the offset into the global offset table at
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/// which the address of a call site relocation entry symbol resides
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/// during execution. This is different from the above since this flag
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/// can only be present in call instructions.
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// MO_GOT_CALL,
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/// MO_GPREL - Represents the offset from the current gp value to be used
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/// for the relocatable object file being produced.
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// MO_GPREL,
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/// MO_ABS_HILO - Represents the hi or low part of an absolute symbol
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/// address.
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// MO_ABS_HILO
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};
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}
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class MBlazeInstrInfo : public TargetInstrInfoImpl {
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MBlazeTargetMachine &TM;
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const MBlazeRegisterInfo RI;
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public:
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explicit MBlazeInstrInfo(MBlazeTargetMachine &TM);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; }
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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/// Branch Analysis
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
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const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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/// Insert nop instruction when hazard condition is found
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned getGlobalBaseReg(MachineFunction *MF) const;
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};
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}
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#endif
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