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3904c8ffec
llvm-mirror/lib/Target/SparcV8
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Brian Gaeke 3904c8ffec Add all the rest of the ADD and SUB variants, some of which are important for 
64-bit support.

llvm-svn: 18087
2004-11-21 07:13:17 +00:00
..
DelaySlotFiller.cpp Use TargetMachine::hasDelaySlot() instead of our old switch statement 2004-09-30 04:04:47 +00:00
FPMover.cpp Pass which converts FpMOVD (double move pseudoinstructions) to pairs 2004-09-29 03:24:34 +00:00
Makefile Change name of target lib to conform to new naming scheme. 2004-10-29 21:57:16 +00:00
README.txt Update to-do list. 2004-11-21 07:13:15 +00:00
SparcV8.h Add createSparcV8FPMoverPass(). 2004-09-29 03:25:39 +00:00
SparcV8.td Prettify formatting of the file, adjust paths to making V8 a subdir of Sparc 2004-09-22 20:09:29 +00:00
SparcV8AsmPrinter.cpp Handle GhostLinkage case for completeness (should not be seen by the asm writer) 2004-11-19 21:49:19 +00:00
SparcV8CodeEmitter.cpp * Add baseline structural JIT code, but disable the JIT to allow llvm-gcc builds 2004-10-19 19:49:42 +00:00
SparcV8InstrFormats.td Class F2_1 already inherits the imm22 field from class F2 2004-10-14 22:32:24 +00:00
SparcV8InstrInfo.cpp Recognize FpMOVD as a move. 2004-09-29 16:45:47 +00:00
SparcV8InstrInfo.h
SparcV8InstrInfo.td Add all the rest of the ADD and SUB variants, some of which are important for 2004-11-21 07:13:17 +00:00
SparcV8ISelSimple.cpp Support add, sub, mul, div, rem on longs/ulongs (latter 3 by emitting libcalls). 2004-11-21 07:13:16 +00:00
SparcV8JITInfo.h
SparcV8RegisterInfo.cpp Remove dependency on MRegisterInfo::getRegClass 2004-10-29 21:42:27 +00:00
SparcV8RegisterInfo.h
SparcV8RegisterInfo.td Allocate fewer registers and tighten up alignment restrictions. 2004-11-18 00:25:20 +00:00
SparcV8TargetMachine.cpp Allocate fewer registers and tighten up alignment restrictions. 2004-11-18 00:25:20 +00:00
SparcV8TargetMachine.h Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the 2004-10-09 05:57:01 +00:00

README.txt 

SparcV8 backend skeleton
------------------------

This directory houses a 32-bit SPARC V8 backend employing an expander-based
instruction selector.  It is not yet functionally complete.  Watch
this space for more news coming soon!

Current expected test failures
------------------------------

All SingleSource/Benchmarks tests are expected to pass.  Currently, all
C++ tests are expected to fail.  Here are the known SingleSource failures:

	UnitTests/SetjmpLongjmp/C++/C++Catch
	UnitTests/SetjmpLongjmp/C++/SimpleC++Test
	Regression/C++/EH/ConditionalExpr
	Regression/C++/EH/ctor_dtor_count-2
	Regression/C++/EH/ctor_dtor_count
	Regression/C++/EH/exception_spec_test
	Regression/C++/EH/function_try_block
	Regression/C++/EH/simple_rethrow
	Regression/C++/EH/simple_throw
	Regression/C++/EH/throw_rethrow_test
	CustomChecked/oopack_v1p8

To-do
-----

* support setcc on longs
* support shifts on longs
* support casting 64-bit integers to FP types
* support FP rem

$Date$