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285 lines
7.7 KiB
C++
285 lines
7.7 KiB
C++
//===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the Hexagon target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
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#include "HexagonDepITypes.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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namespace llvm {
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/// HexagonII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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namespace HexagonII {
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unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY;
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unsigned const TypeCVI_LAST = TypeCVI_ZW;
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enum AddrMode {
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NoAddrMode = 0, // No addressing mode
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Absolute = 1, // Absolute addressing mode
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AbsoluteSet = 2, // Absolute set addressing mode
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BaseImmOffset = 3, // Indirect with offset
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BaseLongOffset = 4, // Indirect with long offset
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BaseRegOffset = 5, // Indirect with register offset
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PostInc = 6 // Post increment addressing mode
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};
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enum MemAccessSize {
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NoMemAccess = 0,
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ByteAccess,
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HalfWordAccess,
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WordAccess,
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DoubleWordAccess,
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HVXVectorAccess
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};
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// MCInstrDesc TSFlags
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// *** Must match HexagonInstrFormat*.td ***
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enum {
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// This 7-bit field describes the insn type.
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TypePos = 0,
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TypeMask = 0x7f,
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// Solo instructions.
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SoloPos = 7,
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SoloMask = 0x1,
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// Packed only with A or X-type instructions.
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SoloAXPos = 8,
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SoloAXMask = 0x1,
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// Only A-type instruction in first slot or nothing.
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RestrictSlot1AOKPos = 9,
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RestrictSlot1AOKMask = 0x1,
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// Predicated instructions.
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PredicatedPos = 10,
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PredicatedMask = 0x1,
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PredicatedFalsePos = 11,
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PredicatedFalseMask = 0x1,
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PredicatedNewPos = 12,
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PredicatedNewMask = 0x1,
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PredicateLatePos = 13,
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PredicateLateMask = 0x1,
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// New-Value consumer instructions.
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NewValuePos = 14,
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NewValueMask = 0x1,
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// New-Value producer instructions.
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hasNewValuePos = 15,
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hasNewValueMask = 0x1,
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// Which operand consumes or produces a new value.
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NewValueOpPos = 16,
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NewValueOpMask = 0x7,
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// Stores that can become new-value stores.
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mayNVStorePos = 19,
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mayNVStoreMask = 0x1,
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// New-value store instructions.
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NVStorePos = 20,
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NVStoreMask = 0x1,
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// Loads that can become current-value loads.
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mayCVLoadPos = 21,
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mayCVLoadMask = 0x1,
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// Current-value load instructions.
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CVLoadPos = 22,
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CVLoadMask = 0x1,
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// Extendable insns.
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ExtendablePos = 23,
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ExtendableMask = 0x1,
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// Insns must be extended.
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ExtendedPos = 24,
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ExtendedMask = 0x1,
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// Which operand may be extended.
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ExtendableOpPos = 25,
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ExtendableOpMask = 0x7,
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// Signed or unsigned range.
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ExtentSignedPos = 28,
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ExtentSignedMask = 0x1,
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// Number of bits of range before extending operand.
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ExtentBitsPos = 29,
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ExtentBitsMask = 0x1f,
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// Alignment power-of-two before extending operand.
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ExtentAlignPos = 34,
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ExtentAlignMask = 0x3,
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CofMax1Pos = 36,
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CofMax1Mask = 0x1,
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CofRelax1Pos = 37,
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CofRelax1Mask = 0x1,
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CofRelax2Pos = 38,
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CofRelax2Mask = 0x1,
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RestrictNoSlot1StorePos = 39,
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RestrictNoSlot1StoreMask = 0x1,
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// Addressing mode for load/store instructions.
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AddrModePos = 42,
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AddrModeMask = 0x7,
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// Access size for load/store instructions.
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MemAccessSizePos = 45,
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MemAccesSizeMask = 0xf,
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// Branch predicted taken.
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TakenPos = 49,
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TakenMask = 0x1,
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// Floating-point instructions.
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FPPos = 50,
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FPMask = 0x1,
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// New-Value producer-2 instructions.
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hasNewValuePos2 = 52,
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hasNewValueMask2 = 0x1,
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// Which operand consumes or produces a new value.
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NewValueOpPos2 = 53,
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NewValueOpMask2 = 0x7,
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// Accumulator instructions.
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AccumulatorPos = 56,
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AccumulatorMask = 0x1,
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// Complex XU, prevent xu competition by preferring slot3
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PrefersSlot3Pos = 57,
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PrefersSlot3Mask = 0x1,
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// v65
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HasTmpDstPos = 60,
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HasTmpDstMask = 0x1,
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CVINewPos = 62,
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CVINewMask = 0x1,
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isCVIPos = 63,
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isCVIMask = 0x1,
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};
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// *** The code above must match HexagonInstrFormat*.td *** //
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// Hexagon specific MO operand flag mask.
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enum HexagonMOTargetFlagVal {
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// Hexagon-specific MachineOperand target flags.
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//
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// When changing these, make sure to update
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// getSerializableDirectMachineOperandTargetFlags and
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// getSerializableBitmaskMachineOperandTargetFlags if needed.
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MO_NO_FLAG,
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/// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
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/// Used for computing a global address for PIC compilations
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MO_PCREL,
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/// MO_GOT - Indicates a GOT-relative relocation
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MO_GOT,
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// Low or high part of a symbol.
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MO_LO16,
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MO_HI16,
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// Offset from the base of the SDA.
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MO_GPREL,
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// MO_GDGOT - indicates GOT relative relocation for TLS
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// GeneralDynamic method
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MO_GDGOT,
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// MO_GDPLT - indicates PLT relative relocation for TLS
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// GeneralDynamic method
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MO_GDPLT,
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// MO_IE - indicates non PIC relocation for TLS
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// Initial Executable method
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MO_IE,
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// MO_IEGOT - indicates PIC relocation for TLS
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// Initial Executable method
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MO_IEGOT,
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// MO_TPREL - indicates relocation for TLS
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// local Executable method
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MO_TPREL,
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// HMOTF_ConstExtended
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// Addendum to above, indicates a const extended op
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// Can be used as a mask.
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HMOTF_ConstExtended = 0x80,
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// Union of all bitmasks (currently only HMOTF_ConstExtended).
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MO_Bitmasks = HMOTF_ConstExtended
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};
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// Hexagon Sub-instruction classes.
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enum SubInstructionGroup {
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HSIG_None = 0,
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HSIG_L1,
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HSIG_L2,
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HSIG_S1,
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HSIG_S2,
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HSIG_A,
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HSIG_Compound
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};
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// Hexagon Compound classes.
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enum CompoundGroup {
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HCG_None = 0,
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HCG_A,
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HCG_B,
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HCG_C
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};
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enum InstParseBits {
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INST_PARSE_MASK = 0x0000c000,
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INST_PARSE_PACKET_END = 0x0000c000,
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INST_PARSE_LOOP_END = 0x00008000,
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INST_PARSE_NOT_END = 0x00004000,
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INST_PARSE_DUPLEX = 0x00000000,
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INST_PARSE_EXTENDER = 0x00000000
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};
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enum InstIClassBits : unsigned {
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INST_ICLASS_MASK = 0xf0000000,
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INST_ICLASS_EXTENDER = 0x00000000,
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INST_ICLASS_J_1 = 0x10000000,
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INST_ICLASS_J_2 = 0x20000000,
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INST_ICLASS_LD_ST_1 = 0x30000000,
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INST_ICLASS_LD_ST_2 = 0x40000000,
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INST_ICLASS_J_3 = 0x50000000,
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INST_ICLASS_CR = 0x60000000,
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INST_ICLASS_ALU32_1 = 0x70000000,
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INST_ICLASS_XTYPE_1 = 0x80000000,
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INST_ICLASS_LD = 0x90000000,
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INST_ICLASS_ST = 0xa0000000,
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INST_ICLASS_ALU32_2 = 0xb0000000,
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INST_ICLASS_XTYPE_2 = 0xc0000000,
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INST_ICLASS_XTYPE_3 = 0xd0000000,
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INST_ICLASS_XTYPE_4 = 0xe0000000,
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INST_ICLASS_ALU32_3 = 0xf0000000
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};
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LLVM_ATTRIBUTE_UNUSED
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static unsigned getMemAccessSizeInBytes(MemAccessSize S) {
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switch (S) {
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case ByteAccess: return 1;
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case HalfWordAccess: return 2;
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case WordAccess: return 4;
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case DoubleWordAccess: return 8;
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default: return 0;
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}
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}
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} // end namespace HexagonII
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
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