Igor Kudrin 7fb2900382 [llvm-objdump] Prefix memory operand addresses with '0x' ... This helps to avoid ambiguity when the address contains only digits 0..9. Differential Revision: https://reviews.llvm.org/D104909		2021-06-28 14:25:21 +07:00
..
AArch64	[AArch64][X86] Allow 64-bit label differences lower to IMAGE_REL_*_REL32	2021-06-21 14:32:25 -07:00
AMDGPU	[AMDGPU] Add gfx1035 target	2021-06-24 14:32:41 -04:00
ARM	Revert "[NFC] remove explicit default value for strboolattr attribute in tests"	2021-05-24 19:43:40 +02:00
AsmParser	[MC] Add MCAsmParser::parseComma to improve diagnostics	2021-05-04 14:13:19 -07:00
AVR	[AVR] Add register aliases XL, YH, etc	2021-03-03 15:36:05 +01:00
BPF
COFF	[AArch64][X86] Allow 64-bit label differences lower to IMAGE_REL_*_REL32	2021-06-21 14:32:25 -07:00
CSKY	[CSKY 6/n] Add support branch and symbol series instruction	2021-04-20 15:36:49 +08:00
Disassembler	[AMDGPU] Add gfx1035 target	2021-06-24 14:32:41 -04:00
ELF	[MC][ELF] Change SHT_LLVM_CALL_GRAPH_PROFILE relocations from SHT_RELA to SHT_REL	2021-06-24 21:35:48 -07:00
Hexagon	Revert "[NFC] remove explicit default value for strboolattr attribute in tests"	2021-05-24 19:43:40 +02:00
Lanai
M68k	[M68k][test][NFC] Scrubing some tests	2021-05-05 17:48:28 -07:00
MachO	Revert "[NFC] remove explicit default value for strboolattr attribute in tests"	2021-05-24 19:43:40 +02:00
Mips	[MC] Remove unneeded "in '.xxx' directive" from diagnostics	2021-05-04 13:30:29 -07:00
MSP430
PowerPC	[PowerPC] Export 16 byte load-store instructions	2021-06-15 01:56:10 +00:00
RISCV	RISCV: simplify a test case for RISCV (NFCI)	2021-06-18 08:19:16 -07:00
Sparc	[SPARC] recognize the "rd %pc, reg" special form	2021-05-23 22:52:59 +02:00
SystemZ	[SystemZ] Add support for .reloc assembler directive	2021-06-25 21:51:10 +02:00
VE
WebAssembly	[WebAssembly] Rename event to tag	2021-06-17 20:34:19 -07:00
X86	[llvm-objdump] Prefix memory operand addresses with '0x'	2021-06-28 14:25:21 +07:00