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313 lines
10 KiB
C++
313 lines
10 KiB
C++
//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
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#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "MipsFrameLowering.h"
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#include "MipsISelLowering.h"
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#include "MipsInstrInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "MipsGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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class MipsTargetMachine;
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class MipsSubtarget : public MipsGenSubtargetInfo {
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virtual void anchor();
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enum MipsArchEnum {
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MipsDefault,
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Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
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Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
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};
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enum class CPU { P5600 };
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// Mips architecture version
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MipsArchEnum MipsArchVersion;
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// Processor implementation (unused but required to exist by
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// tablegen-erated code).
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CPU ProcImpl;
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// IsLittle - The target is Little Endian
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bool IsLittle;
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// IsSoftFloat - The target does not support any floating point instructions.
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bool IsSoftFloat;
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// IsSingleFloat - The target only supports single precision float
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// point operations. This enable the target to use all 32 32-bit
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// floating point registers instead of only using even ones.
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bool IsSingleFloat;
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// IsFPXX - MIPS O32 modeless ABI.
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bool IsFPXX;
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// NoABICalls - Disable SVR4-style position-independent code.
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bool NoABICalls;
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// IsFP64bit - The target processor has 64-bit floating point registers.
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bool IsFP64bit;
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/// Are odd single-precision registers permitted?
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/// This corresponds to -modd-spreg and -mno-odd-spreg
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bool UseOddSPReg;
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// IsNan2008 - IEEE 754-2008 NaN encoding.
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bool IsNaN2008bit;
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// IsFP64bit - General-purpose registers are 64 bits wide
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bool IsGP64bit;
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// HasVFPU - Processor has a vector floating point unit.
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bool HasVFPU;
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// CPU supports cnMIPS (Cavium Networks Octeon CPU).
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bool HasCnMips;
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// isLinux - Target system is Linux. Is false we consider ELFOS for now.
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bool IsLinux;
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// UseSmallSection - Small section is used.
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bool UseSmallSection;
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/// Features related to the presence of specific instructions.
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// HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
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bool HasMips3_32;
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// HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
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bool HasMips3_32r2;
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// HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
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bool HasMips4_32;
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// HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
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bool HasMips4_32r2;
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// HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
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bool HasMips5_32r2;
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// InMips16 -- can process Mips16 instructions
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bool InMips16Mode;
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// Mips16 hard float
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bool InMips16HardFloat;
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// PreviousInMips16 -- the function we just processed was in Mips 16 Mode
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bool PreviousInMips16Mode;
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// InMicroMips -- can process MicroMips instructions
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bool InMicroMipsMode;
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// HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
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bool HasDSP, HasDSPR2, HasDSPR3;
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// Allow mixed Mips16 and Mips32 in one source file
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bool AllowMixed16_32;
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// Optimize for space by compiling all functions as Mips 16 unless
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// it needs floating point. Functions needing floating point are
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// compiled as Mips32
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bool Os16;
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// HasMSA -- supports MSA ASE.
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bool HasMSA;
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// UseTCCInDIV -- Enables the use of trapping in the assembler.
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bool UseTCCInDIV;
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// HasEVA -- supports EVA ASE.
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bool HasEVA;
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InstrItineraryData InstrItins;
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// We can override the determination of whether we are in mips16 mode
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// as from the command line
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enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
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const MipsTargetMachine &TM;
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Triple TargetTriple;
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const SelectionDAGTargetInfo TSInfo;
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std::unique_ptr<const MipsInstrInfo> InstrInfo;
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std::unique_ptr<const MipsFrameLowering> FrameLowering;
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std::unique_ptr<const MipsTargetLowering> TLInfo;
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public:
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/// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
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bool enablePostRAScheduler() const override;
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void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
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CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
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/// Only O32 and EABI supported right now.
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bool isABI_EABI() const;
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bool isABI_N64() const;
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bool isABI_N32() const;
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bool isABI_O32() const;
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const MipsABIInfo &getABI() const;
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bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
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bool little, const MipsTargetMachine &TM);
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool hasMips1() const { return MipsArchVersion >= Mips1; }
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bool hasMips2() const { return MipsArchVersion >= Mips2; }
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bool hasMips3() const { return MipsArchVersion >= Mips3; }
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bool hasMips4() const { return MipsArchVersion >= Mips4; }
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bool hasMips5() const { return MipsArchVersion >= Mips5; }
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bool hasMips4_32() const { return HasMips4_32; }
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bool hasMips4_32r2() const { return HasMips4_32r2; }
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bool hasMips32() const {
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return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
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hasMips64();
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}
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bool hasMips32r2() const {
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return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
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hasMips64r2();
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}
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bool hasMips32r3() const {
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return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
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hasMips64r2();
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}
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bool hasMips32r5() const {
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return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
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hasMips64r5();
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}
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bool hasMips32r6() const {
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return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
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hasMips64r6();
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}
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bool hasMips64() const { return MipsArchVersion >= Mips64; }
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bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
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bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
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bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
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bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
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bool hasCnMips() const { return HasCnMips; }
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bool isLittle() const { return IsLittle; }
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bool isABICalls() const { return !NoABICalls; }
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bool isFPXX() const { return IsFPXX; }
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bool isFP64bit() const { return IsFP64bit; }
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bool useOddSPReg() const { return UseOddSPReg; }
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bool noOddSPReg() const { return !UseOddSPReg; }
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bool isNaN2008() const { return IsNaN2008bit; }
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bool isGP64bit() const { return IsGP64bit; }
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bool isGP32bit() const { return !IsGP64bit; }
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unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
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bool isSingleFloat() const { return IsSingleFloat; }
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bool hasVFPU() const { return HasVFPU; }
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bool inMips16Mode() const { return InMips16Mode; }
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bool inMips16ModeDefault() const {
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return InMips16Mode;
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}
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// Hard float for mips16 means essentially to compile as soft float
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// but to use a runtime library for soft float that is written with
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// native mips32 floating point instructions (those runtime routines
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// run in mips32 hard float mode).
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bool inMips16HardFloat() const {
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return inMips16Mode() && InMips16HardFloat;
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}
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bool inMicroMipsMode() const { return InMicroMipsMode; }
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bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
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bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
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bool hasDSP() const { return HasDSP; }
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bool hasDSPR2() const { return HasDSPR2; }
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bool hasDSPR3() const { return HasDSPR3; }
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bool hasMSA() const { return HasMSA; }
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bool hasEVA() const { return HasEVA; }
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bool useSmallSection() const { return UseSmallSection; }
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bool hasStandardEncoding() const { return !inMips16Mode(); }
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bool useSoftFloat() const { return IsSoftFloat; }
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bool enableLongBranchPass() const {
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return hasStandardEncoding() || allowMixed16_32();
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}
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/// Features related to the presence of specific instructions.
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bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
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bool hasMTHC1() const { return hasMips32r2(); }
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bool allowMixed16_32() const { return inMips16ModeDefault() |
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AllowMixed16_32; }
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bool os16() const { return Os16; }
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bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
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// for now constant islands are on for the whole compilation unit but we only
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// really use them if in addition we are in mips16 mode
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static bool useConstantIslands();
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unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
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// Grab relocation model
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Reloc::Model getRelocationModel() const;
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MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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const TargetMachine &TM);
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/// Does the system support unaligned memory access.
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///
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/// MIPS32r6/MIPS64r6 require full unaligned access support but does not
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/// specify which component of the system provides it. Hardware, software, and
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/// hybrid implementations are all valid.
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bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
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// Set helper classes
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void setHelperClassesMips16();
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void setHelperClassesMipsSE();
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
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const TargetFrameLowering *getFrameLowering() const override {
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return FrameLowering.get();
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}
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const MipsRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo->getRegisterInfo();
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}
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const MipsTargetLowering *getTargetLowering() const override {
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return TLInfo.get();
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}
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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};
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} // End llvm namespace
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#endif
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