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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 13:02:52 +02:00
llvm-mirror/test/CodeGen
Jan Vesely ba1aea29ff AMDGPU/R600: Add implicitarg.ptr intrinsic
Differential Revision: http://reviews.llvm.org/D21622

llvm-svn: 275024
2016-07-10 21:20:29 +00:00
..
AArch64 VirtRegMap: Replace some identity copies with KILL instructions. 2016-07-09 00:19:07 +00:00
AMDGPU AMDGPU/R600: Add implicitarg.ptr intrinsic 2016-07-10 21:20:29 +00:00
ARM Do not expand SDIV when compiling for minimum code size 2016-07-08 15:32:01 +00:00
BPF
Generic
Hexagon
Inputs
Lanai [lanai] Use peephole optimizer to generate more conditional ALU operations. 2016-07-07 23:36:04 +00:00
Mips
MIR [lanai] Update test to use peephole-opt and not peephole-opts 2016-07-08 22:28:29 +00:00
MSP430
NVPTX NVPTX: Remove the legacy ptx intrinsics 2016-07-07 16:40:17 +00:00
PowerPC VirtRegMap: Replace some identity copies with KILL instructions. 2016-07-09 00:19:07 +00:00
SPARC VirtRegMap: Replace some identity copies with KILL instructions. 2016-07-09 00:19:07 +00:00
SystemZ [SystemZ] Utilize Test Data Class instructions. 2016-07-10 14:41:22 +00:00
Thumb [Thumb] Reapply r272251 with a fix for PR28348 (mk 2) 2016-07-05 12:37:13 +00:00
Thumb2 [Thumb] Reapply r272251 with a fix for PR28348 (mk 2) 2016-07-05 12:37:13 +00:00
WebAssembly
WinEH
X86 [X86][SSE] Add support for target shuffle combining to PSHUFLW/PSHUFHW 2016-07-10 21:02:47 +00:00
XCore