mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 21:13:02 +02:00
98be3942ed
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. llvm-svn: 216225
31 lines
705 B
LLVM
31 lines
705 B
LLVM
; RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
|
|
; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
|
|
|
|
define void @store_i8(i8* %a) {
|
|
; CHECK-LABEL: store_i8
|
|
; CHECK: strb wzr, [x0]
|
|
store i8 0, i8* %a
|
|
ret void
|
|
}
|
|
|
|
define void @store_i16(i16* %a) {
|
|
; CHECK-LABEL: store_i16
|
|
; CHECK: strh wzr, [x0]
|
|
store i16 0, i16* %a
|
|
ret void
|
|
}
|
|
|
|
define void @store_i32(i32* %a) {
|
|
; CHECK-LABEL: store_i32
|
|
; CHECK: str wzr, [x0]
|
|
store i32 0, i32* %a
|
|
ret void
|
|
}
|
|
|
|
define void @store_i64(i64* %a) {
|
|
; CHECK-LABEL: store_i64
|
|
; CHECK: str xzr, [x0]
|
|
store i64 0, i64* %a
|
|
ret void
|
|
}
|