Amara Emerson bbd25a9a88 [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions. ... These mirror the IR and SelectionDAG intrinsics & nodes. Opcodes added: G_VECREDUCE_SEQ_FADD G_VECREDUCE_SEQ_FMUL G_VECREDUCE_FADD G_VECREDUCE_FMUL G_VECREDUCE_FMAX G_VECREDUCE_FMIN G_VECREDUCE_ADD G_VECREDUCE_MUL G_VECREDUCE_AND G_VECREDUCE_OR G_VECREDUCE_XOR G_VECREDUCE_SMAX G_VECREDUCE_SMIN G_VECREDUCE_UMAX G_VECREDUCE_UMIN Differential Revision: https://reviews.llvm.org/D88750		2020-10-08 10:33:19 -07:00
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block-extract.png	[globalisel][docs] Add a section about debugging with the block extractor	2019-11-05 14:48:27 -08:00
GenericOpcode.rst	[GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions.	2020-10-08 10:33:19 -07:00
GMIR.rst	[docs] Fix typos	2020-08-09 19:31:49 -07:00
index.rst	[globalisel][docs] Rework GMIR documentation and add an early GenericOpcode reference	2019-11-05 15:16:43 -08:00
InstructionSelect.rst
IRTranslator.rst	Doc: Links should use https	2020-03-22 22:49:33 +01:00
KnownBits.rst	Doc: Links should use https	2020-03-22 22:49:33 +01:00
Legalizer.rst	GlobalISel: Make type for lower action more consistently optional	2020-08-17 16:24:55 -04:00
pipeline-overview-customized.png
pipeline-overview-with-combiners.png
pipeline-overview.png
Pipeline.rst	Try to fix sphinx "Could not lex literal_block as "llvm"" warning.	2019-11-09 22:15:26 +00:00
Porting.rst	[globalisel][docs] Add the tutorial to the Porting document	2019-10-30 14:53:39 -07:00
RegBankSelect.rst
Resources.rst
testing-pass-level.png
testing-unit-level.png