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cd1fb2fd55
The IRTranslator cannot generate these instructions at the moment so there's no issue with not having implemented ISel for them yet. D40092 will add G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* to the IRTranslator and a further patch will add support for lowering G_ATOMIC_CMPXCHG_WITH_SUCCESS into G_ATOMIC_CMPXCHG with an external success check via the `Lower` action. The separation of G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMIC_CMPXCHG is to import SelectionDAG rules while still supporting targets that prefer to custom lower the original LLVM-IR-like operation. llvm-svn: 319216
39 lines
1.3 KiB
C++
39 lines
1.3 KiB
C++
//===- AArch64LegalizerInfo --------------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the Machinelegalizer class for
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/// AArch64.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINELEGALIZER_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINELEGALIZER_H
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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namespace llvm {
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class LLVMContext;
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class AArch64Subtarget;
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/// This class provides the information for the target register banks.
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class AArch64LegalizerInfo : public LegalizerInfo {
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public:
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AArch64LegalizerInfo(const AArch64Subtarget &ST);
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bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const override;
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private:
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bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const;
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};
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} // End llvm namespace.
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#endif
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