Amara Emerson 3e42041b2e [AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load. ... The tablegen imported patterns for sext(load(a)) don't check for single uses of the load or delete the original after matching. As a result two loads are left in the generated code. This particular issue will be fixed by adding support for a G_SEXTLOAD opcode in future. There are however other potential issues around this that wouldn't be fixed by a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile loads at all in the AArch64 selector. Fixes/works around PR36018. llvm-svn: 323371		2018-01-24 20:35:37 +00:00
..
AsmParser	[AArch64][SVE] Asm: PTRUE and PTRUES instructions	2018-01-22 15:29:19 +00:00
Disassembler	Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions	2018-01-09 17:01:27 +00:00
InstPrinter	[AArch64][SVE] Asm: Predicate patterns	2018-01-22 10:46:00 +00:00
MCTargetDesc	Thread MCSubtargetInfo through Target::createMCAsmBackend	2018-01-03 08:53:05 +00:00
TargetInfo	Add backend name to Target to enable runtime info to be fed back into TableGen	2017-11-15 23:55:44 +00:00
Utils	[AArch64][SVE] Asm: Predicate patterns	2018-01-22 10:46:00 +00:00
AArch64.h	[AArch64] Avoid SIMD interleaved store instruction for Exynos.	2017-12-08 00:58:49 +00:00
AArch64.td	AArch64: Cyclone: Remove SlowMisaligned128Store tuning flag	2018-01-24 00:39:53 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64AdvSIMDScalarPass.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64AsmPrinter.cpp	[CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64	2018-01-17 23:55:23 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CallLowering.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64CallLowering.h
AArch64CleanupLocalDynamicTLSPass.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64CollectLOH.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64CondBrTuning.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64ConditionalCompares.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64ConditionOptimizer.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64DeadRegisterDefinitionsPass.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64ExpandPseudoInsts.cpp	Fix a bunch more layering of CodeGen headers that are in Target	2017-11-17 01:07:10 +00:00
AArch64FalkorHWPFFix.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64FastISel.cpp	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
AArch64FrameLowering.cpp	AArch64: Fix emergency spillslot being out of reach for large callframes	2018-01-19 03:16:36 +00:00
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def	[AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies	2017-11-18 04:28:56 +00:00
AArch64InstrAtomics.td	[globalisel][tablegen] Add support for relative AtomicOrderings	2017-11-30 21:05:59 +00:00
AArch64InstrFormats.td	[AArch64][SVE] Asm: Add support for RDVL/ADDVL/ADDPL instructions	2018-01-19 15:22:00 +00:00
AArch64InstrInfo.cpp	[MachineOutliner] Move hasAddressTaken check to MachineOutliner.cpp	2018-01-13 00:42:28 +00:00
AArch64InstrInfo.h	[MachineOutliner] AArch64: Handle instrs that use SP and will never need fixups	2018-01-09 00:26:18 +00:00
AArch64InstrInfo.td	[AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian	2018-01-17 14:39:29 +00:00
AArch64InstructionSelector.cpp	[AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load.	2018-01-24 20:35:37 +00:00
AArch64ISelDAGToDAG.cpp	AArch64: get type from correct result when forming BFX	2018-01-23 15:11:27 +00:00
AArch64ISelLowering.cpp	[AArch64] Avoid unnecessary vector byte-swapping in big-endian	2018-01-24 14:13:47 +00:00
AArch64ISelLowering.h	AArch64: Fix emergency spillslot being out of reach for large callframes	2018-01-19 03:16:36 +00:00
AArch64LegalizerInfo.cpp	Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.	2017-12-05 05:52:07 +00:00
AArch64LegalizerInfo.h	[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal	2017-11-28 20:21:15 +00:00
AArch64LoadStoreOptimizer.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64MachineFunctionInfo.h
AArch64MacroFusion.cpp	Remove redundant includes from lib/Target/AArch64.	2017-12-14 10:36:20 +00:00
AArch64MacroFusion.h
AArch64MCInstLower.cpp	Fix a bunch more layering of CodeGen headers that are in Target	2017-11-17 01:07:10 +00:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp	Rename LiveIntervalAnalysis.h to LiveIntervals.h	2017-12-13 02:51:04 +00:00
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64RegisterBankInfo.cpp	[AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR	2017-11-18 04:28:59 +00:00
AArch64RegisterBankInfo.h
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp	AArch64: Fix emergency spillslot being out of reach for large callframes	2018-01-19 03:16:36 +00:00
AArch64RegisterInfo.h
AArch64RegisterInfo.td	[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.	2018-01-03 10:15:46 +00:00
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedM1.td	[AArch64] Adjust the cost model for Exynos M1 and M2	2017-11-22 22:48:50 +00:00
AArch64SchedThunderX2T99.td	[AArch64] Remove Unsupported = 1 flag for the WriteAtomic WriteRes.	2018-01-11 16:50:56 +00:00
AArch64SchedThunderX.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp	AArch64/X86: Factor out common bzero logic; NFC	2017-12-18 23:14:28 +00:00
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64StorePairSuppress.cpp	MachineFunction: Return reference from getFunction(); NFC	2017-12-15 22:22:58 +00:00
AArch64Subtarget.cpp	AArch64: Fix emergency spillslot being out of reach for large callframes	2018-01-19 03:16:36 +00:00
AArch64Subtarget.h	AArch64: Fix emergency spillslot being out of reach for large callframes	2018-01-19 03:16:36 +00:00
AArch64SVEInstrInfo.td	[AArch64][SVE] Asm: Add support for RDVL/ADDVL/ADDPL instructions	2018-01-19 15:22:00 +00:00
AArch64SystemOperands.td	[AArch64][SVE] Asm: Predicate patterns	2018-01-22 10:46:00 +00:00
AArch64TargetMachine.cpp	Add a TargetOption to enable/disable GlobalISel	2018-01-17 22:34:21 +00:00
AArch64TargetMachine.h	(Re-landing) Expose a TargetMachine::getTargetTransformInfo function	2017-12-22 18:21:59 +00:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h	Fix a bunch more layering of CodeGen headers that are in Target	2017-11-17 01:07:10 +00:00
AArch64TargetTransformInfo.cpp	Fix -Wsign-compare warnings on Windows	2018-01-05 19:53:51 +00:00
AArch64TargetTransformInfo.h
CMakeLists.txt	[AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features.	2017-12-08 22:04:13 +00:00
LLVMBuild.txt
SVEInstrFormats.td	[AArch64][SVE] Asm: PTRUE and PTRUES instructions	2018-01-22 15:29:19 +00:00