Amara Emerson 0a9b8a10a9 [AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy ... On AArch64 we generate redundant G_SEXTs or G_SEXT_INREGs because of this. Differential Revision: https://reviews.llvm.org/D81993		2020-07-13 20:27:45 -07:00
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GlobalISel	[AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy	2020-07-13 20:27:45 -07:00
CodeGenCWrappers.h
GenericOpcodes.td	[MachineVerifier][GlobalISel] Check that branches have a MBB operand or are declared indirect. Add missing properties to G_BRJT, G_BRINDIRECT	2020-06-15 11:17:09 +02:00
Target.td	Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.	2020-07-01 12:51:50 -04:00
TargetCallingConv.td	Reland [X86] Codegen for preallocated	2020-05-20 11:25:44 -07:00
TargetInstrPredicate.td
TargetIntrinsicInfo.h	TargetIntrinsicInfo.h - remove unnecessary Compiler.h include. NFC.	2020-05-19 09:28:13 +01:00
TargetItinerary.td	[llvm] NFC: Fix trivial typo in rst and td files	2020-04-23 14:26:32 +09:00
TargetLoweringObjectFile.h	[NFC][XCOFF][AIX] Return function entry point symbol with dedicate function	2020-05-27 17:54:22 +00:00
TargetMachine.h	Options for Basic Block Sections, enabled in D68063 and D73674.	2020-06-02 00:23:32 -07:00
TargetOptions.h	[xray] Option to omit the function index	2020-06-17 13:49:01 -04:00
TargetPfmCounters.td
TargetSchedule.td	[llvm] NFC: Fix trivial typo in rst and td files	2020-04-23 14:26:32 +09:00
TargetSelectionDAG.td	[SDAG] Add new AssertAlign ISD node.	2020-06-23 00:51:11 -04:00