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llvm-mirror/include/llvm/Target/GlobalISel
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Amara Emerson 0a9b8a10a9 [AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy 
On AArch64 we generate redundant G_SEXTs or G_SEXT_INREGs because of this.

Differential Revision: https://reviews.llvm.org/D81993
2020-07-13 20:27:45 -07:00
..
Combine.td [AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy 2020-07-13 20:27:45 -07:00
RegisterBank.td
SelectionDAGCompat.td GlobalISel: Define equivalent nodes for saturating add/sub 2020-07-13 14:46:40 -04:00
Target.td