1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 04:22:57 +02:00
llvm-mirror/test/MC/Mips/mips64r6
Daniel Sanders 556791680d [mips][ias] Range check uimm5 operands and fix several bugs this revealed.
Summary:
The bugs were:
* append, prepend, and balign were not tested
* balign takes a uimm2 not a uimm5.
* drotr32 was correctly implemented with a uimm5 but the tests expected
  '52' to be valid.
* li/la were implemented with a uimm5 instead of simm32. simm32 isn't
  completely correct either but I'll fix that when I get to simm32.

A notable omission are some of the shift instructions. Several of these
have been implemented using a single uimm6 instruction (rather than two
uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated
in the uimm6 patch.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14712

llvm-svn: 254164
2015-11-26 16:35:41 +00:00
..
invalid-mips1-wrong-error.s [mips] Added support for various EVA ASE instructions. 2015-09-15 10:02:16 +00:00
invalid-mips1.s
invalid-mips2.s
invalid-mips3-wrong-error.s [mips] Added support for various EVA ASE instructions. 2015-09-15 10:02:16 +00:00
invalid-mips3.s
invalid-mips4-wrong-error.s [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions 2015-09-16 09:14:35 +00:00
invalid-mips4.s [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions 2015-09-16 09:14:35 +00:00
invalid-mips5-wrong-error.s
invalid-mips5.s
invalid-mips32-wrong-error.s
invalid-mips64.s
invalid.s [mips][ias] Range check uimm5 operands and fix several bugs this revealed. 2015-11-26 16:35:41 +00:00
relocations.s
valid-xfail.s
valid.s [mips][ias] Range check uimm2 operands and fix a bug this revealed. 2015-11-06 12:22:31 +00:00